Processor Assured and Opportunistic Cores Power Management

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Solution Overview

Problem

Modern processors with multiple cores face increased power consumption during multi-threaded workloads, leading to potential faults, failures, and thermal events, limiting performance due to power and thermal constraints.

Innovation Solution

Implementing a processor configuration with 'assured' and 'opportunistic' cores, where assured cores operate within specified power and thermal limits for worst-case workloads, and opportunistic cores are used for lower power workloads, with dynamic frequency adjustment and core shedding to manage power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all cores operate multi-threaded to increase performance, then multi-threaded performance is improved, but power consumption increases undesirably

Engineering Contradiction:
Improvemulti-threaded performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The processor cores are segmented into two distinct categories: assured cores and opportunistic cores. This segmentation allows the system to differentiate between cores that are guaranteed to meet performance targets and those that can be used when power headroom is available, thereby enabling multi-threaded performance improvement without proportionally increasing power consumption of all cores

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processor implements dynamic power management where the operational status of opportunistic cores is adjusted based on real-time power headroom conditions. When power headroom is available, opportunistic cores are activated to enhance multi-threaded performance; when power constraints are detected, these cores are deactivated or frequency-reduced, thus dynamically balancing performance and power consumption

Inventive Principle:
Principle #15Dynamics

2Productivity

If more cores are added to increase multi-threaded performance, then core count is increased, but power dissipation limits are exceeded

Engineering Contradiction:
Improvemulti-threaded performanceVSAvoidpower dissipation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The processor changes the operational parameters of cores based on workload and power conditions. Assured cores maintain guaranteed performance parameters, while opportunistic cores have variable parameters that are adjusted according to available power headroom, allowing the system to increase effective core count for multi-threaded workloads without exceeding power dissipation limits

Inventive Principle:
Principle #35Parameter changes

3Reliability

If assured cores are used for worst-case workloads to guarantee performance, then performance reliability is improved, but the number of available cores for other workloads is reduced

Engineering Contradiction:
Improveperformance guaranteeVSAvoidcore utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting cores into assured and opportunistic categories, the system ensures that assured cores are reserved for worst-case workloads requiring performance guarantees, while opportunistic cores become available for less demanding workloads or as additional capacity when power conditions permit, thus maintaining both performance reliability and overall core utilization

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4421633A1Specifying a processor with assured and opportunistic cores
Publication Date: 2024.08.28 INTEL CORP
  • EP4421633A1 patent drawingFigure 1
  • EP4421633A1 patent drawingFigure 2
  • EP4421633A1 patent drawingFigure 3

AI summary

In one embodiment, a processor includes: a plurality of cores to execute instructions and a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. The processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores, and is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. Other embodiments are described and claimed.