Processor BIST Using ALU Datapath for Fault Coverage
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Solution Overview
Problem
Conventional built-in self-test (BIST) methods for processor chips, such as Logic BIST (LBIST) and Memory BIST (MBIST), face challenges including false path detection, excessive heat generation, crosstalk issues, and limited fault coverage, particularly in advanced semiconductor processes, which can lead to missed defects and increased testing costs.
Innovation Solution
A configurable unit with a memory, ALU, test controller, and signature register is introduced, where the test controller generates and applies test patterns directly to the datapath, compresses results, and stores them as a test signature, allowing for quasi-functional testing that resembles normal operation conditions, thereby enhancing fault coverage without the costs associated with n-detect methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If Logic BIST generates and applies pseudo-random test vectors to scan chains, then testing can be performed with reduced dependence on external tester, but false paths are created that are not used in normal operation leading to false failure detection
Solution Approach 1:
The processor unit tests itself using built-in test controllers that generate test patterns and evaluate results without external intervention. The ALU executes test operations on itself using test data from memory, and the test controller autonomously compresses results and compares them against expected values, enabling the system to self-diagnose defects.
Solution Approach 2:
The ALU serves dual purposes: it performs normal computational operations during product operation and executes test operations during testing. The same ALU hardware that processes legitimate data also processes test patterns, eliminating the need for separate test hardware and ensuring that testing occurs on the actual operational paths without creating false paths.
2Reliability
If Logic BIST increases test activity to improve fault coverage, then more defects can be detected, but excessive heat is generated causing timing violations and functional faults
Solution Approach 1:
Testing is performed periodically or on-demand rather than continuously. The test controller activates test sequences only when needed (e.g., during manufacturing test or self-diagnosis events), allowing the processor to operate normally during other periods. This periodic testing approach achieves sufficient fault coverage without sustaining high heat generation continuously.
Solution Approach 2:
The test controller applies test patterns selectively to specific operational paths within the ALU rather than exercising all possible paths with maximum intensity. By focusing test effort on critical paths and using reasonable test vectors rather than exhaustive testing, sufficient fault coverage is achieved without generating excessive heat that would cause timing violations.
3Reliability
If Logic BIST uses heightened activity during test, then more faults can be detected, but crosstalk issues are caused that are not experienced during normal operation
Solution Approach 1:
The test controller acts as an intermediary that manages test pattern generation and application. It carefully controls the timing and sequence of test vectors, inserting appropriate delays and using controlled signal transitions that minimize simultaneous switching activity. This mediation reduces crosstalk interference while still exercising the operational paths needed for effective defect detection.
4Reliability
If ATPG test vectors are distributed over scan chains, then stuck-at faults can be detected with high coverage, but testing time and costs increase proportionally
Solution Approach 1:
The patent replaces the mechanical scan chain testing mechanism with a functional testing approach using the processor's own operational datapath. Instead of shifting test vectors through scan flip-flops, the test controller generates patterns that flow through the actual ALU operational paths, memory interfaces, and control logic. This substitution maintains high fault coverage for stuck-at faults while dramatically reducing testing time by eliminating scan chain overhead.
5Reliability
If n-detect methods are used to improve fault coverage, then more defects can be detected, but testing costs increase significantly
Solution Approach 1:
The processor unit autonomously performs defect detection using its own computational resources. The test controller generates test patterns, the ALU executes test operations, and the results are compressed and evaluated entirely within the processor unit itself. This self-service approach achieves comprehensive defect detection without requiring complex external testing equipment or multiple detection passes, thereby reducing testing complexity and cost.
Data Source
AI summary
A processor unit includes a memory and an ALU coupled with the memory. The processor unit also comprises a test controller, a test control register, and a signature register. The test controller manages a series of steps to test the processor unit. It overrides an ALU control signal with a replacement ALU control signal, stored in the test control register. It generates a test pattern and writes it to a memory address. It reads memory output data from the memory address, and forwards it to the ALU. The ALU executes an operation on the memory output data based on the replacement ALU control signal. The ALU output provides a test result, which is compressed to obtain a test signature, and stored in the signature register.