Digital Data Processor Bit Extension Circuit
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Solution Overview
Problem
Existing methods for extending the bit width of audio signals, such as JP 2004-180017 A, require large memory capacity and complex processing, making them unsuitable for digital signal processors and consumer appliances that need simplified arithmetic processing and reduced memory usage to generate high-resolution audio signals.
Innovation Solution
A digital data processor that performs weighted addition, arithmetic rightward shift, and bit extension operations to convert an N-bit input signal into an M-bit output signal, using a weighted addition circuit, arithmetic shift circuit, bit extension circuit, and addition circuit, with optional amplification and logarithmic conversion, to generate a signal with increased bit width without referencing stored tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the method of JP 2004-180017 A is used to extend quantization bits, then audio signal resolution is improved, but memory capacity and processing complexity increase significantly
Solution Approach 1:
The patent divides the bit extension process into separate functional stages: weighted addition of time-shifted signals, arithmetic right shift, bit extension with zero-padding, and final addition. This segmentation allows each stage to be implemented with simple dedicated circuits rather than complex unified processing, reducing overall device complexity while maintaining high resolution output
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing weight values for the weighted addition operation, and by pre-determining the number of shifts for the arithmetic right shift operation. This eliminates the need for complex real-time calculations and memory references during actual signal processing, simplifying the processing complexity while preserving audio signal resolution
2Measurement precision
If the method of JP 2004-180017 A is used to extend quantization bits, then audio signal resolution is improved, but memory capacity requirements increase
Solution Approach 1:
The patent extracts and eliminates the need for large memory capacity by replacing the memory-based table reference method with a mathematical approach using weighted addition of time-shifted signals. The weight values are pre-calculated and stored in a small lookup table, and the processing uses only minimal memory for signal buffers, dramatically reducing memory capacity requirements while maintaining high audio signal resolution
Solution Approach 2:
The patent uses copying by creating time-shifted copies of the input signal and combining them through weighted addition. Instead of storing large lookup tables of pre-computed extension values, the system creates multiple copies of the input signal at different time positions and combines them mathematically, reducing memory capacity requirements while achieving the same resolution enhancement
3Reliability
If complex processing methods are used to extend bit width, then audio quality improves, but computational processing becomes too complex for consumer appliances
Solution Approach 1:
The patent replaces complex mechanical-like table lookup and interpolation systems with a mathematical substitution approach using weighted addition and arithmetic shifts. This substitution transforms the processing into simple algebraic operations that can be implemented with basic arithmetic circuits, making the system suitable for consumer appliances while maintaining high audio quality
Solution Approach 2:
The patent changes the processing parameters by using fixed weight values and predetermined shift amounts instead of variable table references. This parameter simplification reduces computational complexity to basic arithmetic operations, making the system feasible for consumer appliances while preserving audio quality through the mathematical equivalence of the transformations
Data Source
AI summary
A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital data processor includes: an weighted addition circuit which is operable to perform weighted addition on at least the input signal and a signal being time-shifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit which is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit which is operable to attach a predetermined bits to an LSD side of the input signal to generate an intermediate signal of M bits; and an addition circuit which is operable to perform addition of the intermediate signal and the processed input signal so as to generate the M-bit output signal.