Processor Bit Matrix Multiplication With Selectable Bitwise Circuits
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Solution Overview
Problem
Processor cores are not optimized for efficient bit-level operations, limiting the support for complex bit matrix multiplication (BMM) operations required in applications like bioinformatics, software defined radio, and cryptology.
Innovation Solution
Implementing BMM instructions that utilize general-purpose registers, packed data registers, or memory-based operands, with selectable multiply and sum circuitry, including bitwise operations such as AND, XOR, and logical/arithmetic operations, to perform bit matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processor cores use general-purpose architecture, then versatility is maintained, but efficiency of bit-level operations deteriorates
Solution Approach 1:
The processor architecture is segmented into general-purpose cores and specialized execution units. The BMM execution unit is a separate segment that handles bit matrix multiplication operations specifically, while general-purpose cores handle other tasks. This segmentation allows each segment to be optimized for its specific function, resolving the contradiction between versatility and bit-level operation efficiency.
Solution Approach 2:
A BMM execution unit acts as an intermediary between general-purpose processor cores and memory/registers. This intermediary unit specializes in bit-level operations and can be called upon by general-purpose cores when BMM operations are needed, allowing the general-purpose architecture to maintain versatility while achieving high efficiency in bit-level operations through the specialized intermediary.
2Productivity
If processor cores are optimized for bit-level operations, then efficiency of bit matrix multiplication improves, but device complexity increases
Solution Approach 1:
The BMM execution unit is designed with multi-functionality to handle various bit matrix operations (multiplication, addition, different data types like bit, byte, word, doubleword). By consolidating multiple bit-level functions into a single execution unit, the processor achieves high efficiency in bit matrix multiplication without proportionally increasing device complexity, as one unit serves multiple purposes.
Solution Approach 2:
The BMM execution unit dynamically adjusts its operation based on input parameters such as data type (bit, byte, word, doubleword), matrix dimensions, and operation type. This dynamic adaptability allows the unit to efficiently handle diverse bit-level operations without requiring separate dedicated hardware for each operation, thereby improving productivity while controlling device complexity.
3Device complexity
If traditional processor architecture is used, then device complexity is kept low, but productivity of bit matrix multiplication deteriorates
Solution Approach 1:
The BMM execution unit is nested within the existing processor architecture as a specialized component. It can be integrated into the existing core structure, sharing resources like caches and registers with general-purpose cores. This nesting approach allows the processor to achieve high productivity in bit matrix multiplication while minimizing the increase in overall device complexity by embedding the specialized unit within the existing architecture rather than creating a completely separate system.
Data Source
AI summary
Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.