Pattern-Recognition Processor Block Disabling for Power Management
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Solution Overview
Problem
Existing pattern recognition systems face bottlenecks due to increasing data volumes and the number of patterns to be identified, leading to performance slowdowns and high power consumption, particularly in hardware designs that require multiple circuits to search data streams for patterns.
Innovation Solution
A pattern-recognition processor with local input conductors that uses parallel finite state machines to evaluate multiple search criteria simultaneously, with block-disabling circuitry to conserve energy by disabling inactive feature cells, allowing efficient searching of data streams without scaling performance with the number of patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple circuits operate in parallel to search data stream for patterns, then pattern recognition performance is improved, but power consumption and heat generation increase proportionally with the number of patterns
Solution Approach 1:
The patent divides the pattern recognition system into multiple banks of content addressable memory (CAM) circuits, where each bank handles a subset of patterns. This segmentation allows parallel processing of multiple patterns while enabling selective activation of only the necessary banks, thereby maintaining high pattern recognition performance while reducing overall power consumption compared to having all circuits active simultaneously.
Solution Approach 2:
The system dynamically activates or deactivates specific CAM banks based on the current search requirements. When searching for patterns in a data stream, only the CAM banks containing relevant patterns are activated, while others remain inactive. This dynamic activation strategy maintains high recognition performance for active patterns while significantly reducing power consumption by keeping inactive banks in a low-power state.
2Productivity
If multiple circuits operate in parallel to search data stream for patterns, then pattern recognition performance is improved, but heat generation increases proportionally with the number of patterns
Solution Approach 1:
By segmenting the pattern recognition system into multiple independent CAM banks, the patent enables spatial distribution of heat generation. Each bank generates heat locally, but the overall heat load is distributed across multiple smaller units rather than concentrated in a single large array, facilitating more effective heat dissipation while maintaining parallel processing performance.
Solution Approach 2:
The dynamic activation of CAM banks directly controls heat generation by ensuring that only the necessary portion of the system is active at any given time. This reduces the total heat generated proportionally to the number of active banks, making thermal management more manageable while preserving pattern recognition performance for the active patterns.
3Use of energy by moving object
If data stream is searched for each pattern one at a time, then power consumption is reduced, but processing delay increases with the number of patterns
Solution Approach 1:
The patent segments the pattern set into multiple CAM banks that can be activated in parallel. This allows the system to process multiple patterns simultaneously rather than sequentially, reducing processing delay while maintaining controlled power consumption through selective activation of only the necessary banks for the current search task.
Solution Approach 2:
Each CAM bank is designed to be universally capable of pattern matching, and multiple banks can be activated simultaneously to handle different patterns. This multi-functionality enables the system to achieve parallel processing of multiple patterns without requiring dedicated hardware for each pattern, thus reducing delay while controlling power consumption through selective activation.
Data Source
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Figure 2
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AI summary
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor (14, 96, 98). In some embodiments, the pattern-recognition processor (14, 96, 98) includes a first block (106) of feature cells (100, 102, 104) coupled to a decoder (28) via a first plurality of local input conductors (120), a first block-disabling circuit (96, 124), and a plurality of global input conductors (119). The pattern-recognition processor (14, 96, 98) further includes a second block (114) of feature cells (108, 110, 122) coupled to the decoder (28) via a second plurality of local input conductors (120), a second block-disabling circuit (98, 126), and the plurality of global input conductors (119).