Multi-Die Processor Boot Coordination via Signal Sequencing
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Solution Overview
Problem
Efficiently booting a processor with multiple sockets and dies is challenging due to the complexity of internal communication and execution of boot procedures, which affects computing efficiency.
Innovation Solution
A processor design where each socket comprises a first and second die, with communication controllers managing memory access through communication buses, allowing coordinated boot procedures across multiple dies to optimize boot time and resource access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple dies execute boot procedures simultaneously, then boot time is reduced, but memory access conflicts occur
Solution Approach 1:
The patent implements preliminary action by having the first die complete its boot procedure and output a boot-completion signal before the second die begins its boot procedure. This sequential triggering mechanism ensures that memory access conflicts are avoided while still enabling parallel boot execution across different die pairs, thereby reducing overall boot time without compromising memory access control reliability
Solution Approach 2:
The patent segments the boot execution into distinct phases across different dies. Each die pair (first die and second die) executes boot procedures in coordinated stages, with the first die completing boot first and then enabling the second die. This segmentation allows parallel boot processing while maintaining proper memory access hierarchy and avoiding conflicts
2Productivity
If first die accesses memory through communication bus and second die, then boot procedure executes, but communication bus becomes bottleneck
Solution Approach 1:
The patent applies preliminary action by having the first die complete its boot procedure and establish memory access patterns before the second die begins accessing memory. This ensures that the communication bus is not simultaneously accessed by multiple dies during critical boot operations, preventing bottlenecks while maintaining boot execution efficiency
Solution Approach 2:
The patent implements dynamic control of the communication bus by using the boot-completion signal from the first die to dynamically enable or disable memory access permissions for the second die. This dynamic switching optimizes bus utilization by ensuring only one die accesses memory at any given time, thereby maintaining high access speeds while enabling parallel boot processing
Data Source
AI summary
A processor includes at least one socket and at least one memory. Each socket includes a first die and a second die. The first die receives a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputs a boot-completion signal after completing the boot procedure. The second die receives the internal boot-enable signal and the boot-completion signal from the first die to execute the boot procedure. The second die is electrically connected to the first die through a communication bus. The memory is electrically connected to the second die. When the first die executes the boot procedure, the first die accesses the memory through the communication bus and the second die.