Processor Branch Cache with Secondary Branch Prediction
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Solution Overview
Problem
Power consumption and latency issues in processor operation due to frequent memory retrieval and instruction fetching, which are constrained by branch prediction accuracy and the need for advanced instruction fetching mechanisms.
Innovation Solution
Incorporating a branch prediction unit with a branch cache and prediction logic module that predicts branch instructions, allowing for the calculation of secondary branch target addresses on the fly without storing them in the cache, and utilizing a prediction table to determine branch directions, thereby optimizing instruction fetching and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If branch target addresses are stored in the branch cache for all branches, then branch prediction accuracy is improved, but the branch cache size and complexity increase
Solution Approach 1:
The patent segments branch information storage into two parts: primary branch target addresses are stored in the branch cache, while secondary branch target addresses are calculated on-the-fly using an address offset. This segmentation reduces the branch cache size by storing only essential information (primary branches and offsets) rather than all possible target addresses, thereby resolving the contradiction between prediction accuracy and cache complexity.
Solution Approach 2:
The patent introduces an address offset as an intermediary value that mediates between the stored primary branch information and the actual secondary branch target address. Instead of storing complete secondary target addresses in the cache, the system stores compact offset values that can be combined with the program counter to derive the actual addresses, reducing cache memory requirements while maintaining prediction capability.
2Productivity
If instructions are fetched in advance based on branch prediction, then processor throughput is improved, but power consumption increases due to frequent memory retrieval
Solution Approach 1:
The patent implements preliminary action by fetching instructions in advance based on predicted branch outcomes. The branch prediction unit determines whether branches will be taken before execution, allowing the instruction fetch unit to proactively retrieve instructions from predicted target addresses. This eliminates pipeline stalls and improves throughput without requiring actual branch execution to occur first.
Solution Approach 2:
The patent extracts only the necessary branch information (target addresses for taken branches, offset for not-taken branches) from the branch cache, rather than retrieving complete branch instruction data. This selective extraction minimizes memory access requirements and reduces the frequency of power-consuming memory retrievals while maintaining effective branch prediction.
3Reliability
If the branch cache stores complete branch information for all branches, then branch prediction accuracy is improved, but latency increases due to longer lookup times
Solution Approach 1:
The patent applies local quality by storing different types of branch information in different locations within the branch cache structure. Primary branch target addresses are stored in one location, while secondary branch information is represented as compact address offsets in another location. This differentiated storage approach optimizes the cache structure for fast lookup of the most frequently accessed information while maintaining complete prediction capability.
Solution Approach 2:
Instead of storing complete target addresses for all branches (the conventional approach), the patent inverts the strategy by storing only primary target addresses and using compact offsets to represent secondary targets. This inversion reduces the amount of data stored in the cache, thereby reducing access latency while maintaining the ability to accurately predict both primary and secondary branch outcomes.
Data Source
AI summary
A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch information stored in the branch cache and the prediction information stored in the prediction table.