Processor Branch Prediction Using Parallel BHT and BTAC Access
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Solution Overview
Problem
Conditional branch instructions in computer processors introduce uncertainty in the instruction pipeline, leading to stalls and delays due to the unpredictability of the next instruction's fetch address, which existing prediction techniques fail to address accurately and timely.
Innovation Solution
A computer processor and data processing method that reads a branch instruction history table (BHT) and branch instruction target address cache (BTAC) in parallel with the current instruction fetch to predict the direction of conditional branch instructions, using override bits to enhance prediction accuracy by considering the branch instruction type, allowing for immediate determination of the next instruction's address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If branch direction prediction is performed after instruction decode and execution, then prediction accuracy is improved, but instruction fetch delay increases significantly
Solution Approach 1:
The patent performs branch direction prediction in advance, during the instruction fetch stage, by reading the branch instruction history table (BHT) and branch instruction target address cache (BTAC) before the instruction is decoded and executed. This preliminary action allows the next instruction to be fetched without waiting for the conditional branch to be resolved, thereby eliminating pipeline stalls while maintaining prediction accuracy through historical data from previous branch executions.
2Loss of time
If branch direction prediction is performed in parallel with instruction fetch, then instruction fetch delay is minimized, but prediction accuracy may be compromised
Solution Approach 1:
The patent introduces an intermediary mechanism consisting of the branch instruction history table (BHT) and branch instruction target address cache (BTAC) that stores historical branch direction information. These intermediaries enable the processor to make accurate predictions during parallel instruction fetch operations by querying pre-stored historical data, thus resolving the contradiction between timing and accuracy.
3Speed
If only dynamic branch history is used for prediction, then prediction speed is improved, but prediction accuracy is reduced
Solution Approach 1:
The patent combines multiple prediction mechanisms into a composite system: the branch instruction history table (BHT) provides dynamic historical branch direction data, the branch instruction target address cache (BTAC) stores pre-computed target addresses for frequently executed branches, and override bits provide static architectural hints. This composite approach leverages both dynamic and static information sources, achieving both speed and accuracy by selecting the most reliable prediction method for each branch instruction type.
Data Source
AI summary
Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.