Processor Buffer Tracking for N-Dimensional Data

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Solution Overview

Problem

Current data processing techniques, such as neural network processing, face inefficiencies in handling and accessing data due to repeated reading and changing dimensionality, which complicates storage and execution of tasks across multiple components.

Innovation Solution

A processor with a handling unit that receives a task with operations in a coordinate space of N=>1 dimensions, utilizing a data structure comprising a partially ordered set of data items, where each item indicates the dimensions for execution and storage, allowing efficient iteration and coordination across components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is read multiple times from storage during neural network processing, then data can be accessed by multiple components, but storage access time and complexity increase

Engineering Contradiction:
Improvedata accessibilityVSAvoidstorage access time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent divides the processing system into multiple independent components (first component, second component, third component) that can process data segments in parallel. Each component has dedicated input and output buffers, allowing data to be processed by multiple components simultaneously without repeated storage access, thus reducing access time while maintaining data accessibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to data flow by implementing multi-dimensional buffers (input buffer, intermediate buffer, output buffer) that allow data to be reused across different time steps and processing stages. This enables components to access data from buffers rather than repeatedly accessing storage, resolving the contradiction between data accessibility and access time.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If data dimensionality changes during processing, then processing flexibility improves, but storage and access complexity increases

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidstorage access complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer management where buffer dimensions and configurations can change during processing. The system dynamically allocates and configures buffers based on the specific dimensionality requirements of different processing stages, allowing flexible adaptation to changing data dimensions without requiring complex static storage structures.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces intermediate buffers as mediator structures between storage and processing components. These buffers act as intermediaries that handle dimensionality transformations and data format conversions, simplifying the interface between storage and multiple processing components while maintaining processing flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple components process data in parallel, then processing speed increases, but coordination and data flow management complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the data flow into distinct channels with dedicated buffers for each processing component. The first component has its own input and intermediate buffers, the second component has separate buffers, and the third component has dedicated output buffers. This segmentation eliminates the need for complex coordination mechanisms while enabling parallel processing, as each component operates independently on its assigned data segments.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240248755A1Tracking buffer reduction and reuse in a processor
Publication Date: 2024.07.25 ARM LTD
  • US20240248755A1 patent drawing
  • US20240248755A1 patent drawing
  • US20240248755A1 patent drawing

AI summary

A processor comprising: a handling unit; a plurality of components each configured to execute a function. The handling unit can receive a task comprising operations on data in a coordinate space having N dimensions, receive a data structure describing execution of the task and comprising a partially ordered set of data items each associated with instructions usable by the plurality of components when executing the task, each data item is associated with a component among the plurality of components, each data item indicates dimensions of the coordinates space for which changes of coordinate causes the function of the associated component to execute, and dimensions of the coordinate space for which changes of coordinate causes the function of the associated component to store data ready to be used by another component. The handling unit iterates over the coordinate space and executes the task using the partially ordered set of data items.