Processor Bus Power Controller for Latency-Constrained Idle Management
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Solution Overview
Problem
Current methods for reducing power consumption in electronic devices, such as mobile computing devices, are inefficient during short periods of processor idle time, as they require high latency to enter advanced power-saving states like C2 and C3, leading to continued high power consumption in the high speed bus interface.
Innovation Solution
A power controller monitors the processor bus for inactivity and transitions the processor interface to a lower power consumption mode, inhibiting new requests and conserving power by temporarily powering down components, independent of the processor or operating system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor enters advanced power-saving states (C2/C3), then power consumption is reduced, but latency increases significantly
Solution Approach 1:
The invention segments the power management function by introducing an intermediate power state for the high speed bus interface that is independent of the processor's power state. This allows the bus interface to be managed separately, enabling shorter idle periods to trigger power savings without requiring the processor to enter high-latency states.
Solution Approach 2:
The invention performs preliminary action by having the high speed bus interface enter a lower power consumption mode before the processor would normally need to exit from sleep state. This proactive power management allows the interface to be ready when needed, reducing overall system latency while maintaining power savings.
2Speed
If the high speed bus interface remains in high power consumption mode, then responsiveness is improved, but power consumption increases
Solution Approach 1:
The invention makes the power consumption mode of the high speed bus interface dynamic by continuously monitoring processor idle time and automatically transitioning between high and low power consumption modes. This dynamic adaptation allows the system to optimize between responsiveness and power consumption based on actual usage patterns.
Solution Approach 2:
The invention changes the power consumption parameter of the high speed bus interface based on monitored idle time thresholds. When idle time exceeds a threshold, the interface transitions to lower power consumption mode; when idle time is short, it remains in high power consumption mode to maintain responsiveness.
3Loss of energy
If resource hibernation is used for the processor interface, then power consumption is reduced, but request processing capability is lost during idle periods
Solution Approach 1:
The invention applies partial action by implementing resource hibernation only for the high speed bus interface while keeping the processor operational. This selective approach allows the interface to save power during idle periods while the processor remains ready to process requests immediately, maintaining overall system productivity without complete system hibernation.
Data Source
AI summary
In an electronic device including a processor interface and a processor interconnected to the processor interface by a bus, activity on the bus is monitored and in response to inactivity, the processor interface is placed in a lower power consumption mode. While in the lower power consumption mode, processor requests to the processor interface are inhibited.