Multi-core Processor Cache Coherency via Software Memory Protocol
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-core processor systems face challenges in maintaining cache coherency without increasing chip area and power consumption, particularly when direct access to physical memory without using cache is required, which complicates hardware development and increases costs.
Innovation Solution
A multi-core processor system that employs a software mechanism to manage cache coherency through a Memory Access Protocol (MAP) with defined states (UNMANAGED, INVALID, PRIVATE, PUBLIC, and PROTECTED) and functions like allocate_private_memory, free_private_memory, and enter_memory_access_protocol, allowing transitions between these states to maintain cache coherency without a shadow area, thereby reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware mechanism is used to maintain cache coherency, then cache coherency is maintained, but chip area and power consumption increase
Solution Approach 1:
The patent replaces the hardware-based cache coherency mechanism with a software-based memory access protocol. The MAP manages cache coherency through software control of memory access rights and states, eliminating the need for additional hardware coherence management circuitry and reducing chip area while maintaining coherency.
Solution Approach 2:
The patent changes the state management approach by introducing multiple memory access states (UNMANAGED, INVALID, PRIVATE, PUBLIC, PROTECTED) that can be dynamically transitioned between. This state-based parameter system allows flexible cache coherency management through software rather than fixed hardware mechanisms.
2Adaptability or versatility
If direct access to physical memory without cache is enabled, then memory access flexibility is improved, but cache coherency maintenance becomes more complex
Solution Approach 1:
The MAP serves as an intermediary software layer between the processor cores and physical memory. It mediates memory access by managing the five defined states and controlling when cache access is permitted versus when direct physical memory access is required, thereby maintaining coherency while enabling flexible memory access patterns.
Solution Approach 2:
The patent implements dynamic state transitions in the memory access protocol, allowing the system to adaptively switch between different access modes (cached vs. direct memory access) based on operational requirements. This dynamic approach maintains coherency complexity manageable while providing access flexibility.
3Area of stationary object
If software-based cache coherency maintenance is implemented, then chip area is reduced, but implementation complexity increases
Solution Approach 1:
The patent segments the memory access management into distinct states (UNMANAGED, INVALID, PRIVATE, PUBLIC, PROTECTED), each with specific access rights and behaviors. This segmentation simplifies the software implementation by breaking down the complex coherency management into manageable, discrete state transitions and access control rules.
4Productivity
If cache accesses are used for all memory access, then data sharing efficiency is improved, but memory access versatility is reduced
Solution Approach 1:
The patent enables dynamic selection between cache access and direct physical memory access based on the memory state. When a memory region is in PRIVATE or PROTECTED state, cache access is used for efficient data sharing. When in PUBLIC or UNMANAGED state, direct memory access is required for versatility, allowing the system to adapt to different performance and versatility requirements.
Data Source
AI summary
According to one embodiment, a state manager classifies an area allocated to the multi-core processor in a first memory area into one of a first state in which allocation to processor cores is not performed, a second state in which allocation to one of the processor cores is performed and read and write are performed, and a third state in which allocation to one or more of the processor cores is performed and read and write are prohibited, and further performs a transition from one of the first state, the second state, and the third state to another. A cache/memory manager writes back a corresponding cache when the state manager performs the transition from the second state to the third state.