Processor Cache Contention Tracking for Coherence Overhead Reduction
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Solution Overview
Problem
Existing processor cache systems face performance bottlenecks due to memory contention, where multiple threads compete to access data, leading to increased cache coherence overhead and reduced access speed.
Innovation Solution
The technology tracks contention in memory locations by using data structures to identify contentious areas, allowing the processor to manage cache operations by storing data in shared or private caches based on contention status, and prioritizing memory operations to reduce lock acquisition time and cache coherence overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple threads access data in memory through shared cache, then data sharing is enabled, but cache coherence overhead increases and access speed decreases
Solution Approach 1:
The patent applies local quality by differentiating cache management based on contention status. Contentious memory locations are managed differently from non-contentious locations: contentious locations use shared cache with single copy, while non-contentious locations use private cache with multiple copies. This localized differentiation reduces overall cache coherence overhead while maintaining data sharing capability where needed.
Solution Approach 2:
The patent segments memory locations into contentious and non-contentious categories using a contention table. This segmentation allows the system to apply different cache management strategies to different segments, reducing the scope of cache coherence protocols to only where necessary and improving overall system performance.
2Productivity
If data is stored in shared cache for multiple threads, then memory access is centralized, but the number of cache copies increases and access speed decreases
Solution Approach 1:
The patent implements dynamic cache management where the number of cache copies is adjusted based on real-time contention status. When contention is detected, the system reduces the number of copies by evicting from private caches and storing only in shared cache. When contention subsides, copies are restored. This dynamic adaptation optimizes both access efficiency and copy quantity.
Solution Approach 2:
The patent changes the parameter of cache copy quantity based on contention metrics. By monitoring contention and adjusting the number of cache copies accordingly, the system optimizes memory access efficiency while minimizing redundant copies. This parameter change is implemented through selective eviction and allocation based on contention table data.
3Reliability
If threads wait for lock acquisition to access contentious data, then data integrity is maintained, but access time increases and performance decreases
Solution Approach 1:
The patent performs preliminary action by proactively detecting contention and pre-evicting data from private caches before conflicts occur. This preliminary eviction prevents future contention by ensuring that when a memory location is identified as contentious, only one copy exists in the shared cache, eliminating the need for threads to wait for lock acquisition.
Solution Approach 2:
The patent enables threads to skip lock acquisition delays by using the contention table to identify non-contentious memory locations. For these locations, threads can directly access data without acquiring locks, rushing through the access process without the overhead of synchronization mechanisms, thereby reducing access time while maintaining integrity for contentious locations.
Data Source
AI summary
The technology disclosed herein involves tracking contention and using the tracked contention to manage processor cache. The technology can be implemented in a processor's cache controlling logic and can enable the processor to track which locations in main memory are contentious. The technology can use the contentiousness of locations to determine where to store the data in cache and how to allocate and evict cache lines in the cache. In one example, the technology can store the data in a shared cache when the location is contentious and can bypass the shared cache and store the data in the private cache when the location is uncontentious. This may be advantageous because storing the data in shared cache can reduce or avoid having multiple copies in different private caches and can reduce the cache coherency overhead involved to keep copies in the private caches in sync.