Processor Cache Dirty Bit Granularity for Bandwidth Reduction
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Solution Overview
Problem
In advanced processor designs, particularly in chip multiprocessor (CMP) architectures, limited off-chip bandwidth is inefficiently used due to frequent writes of redundant data from cache to main memory, leading to unnecessary bandwidth consumption.
Innovation Solution
The technique involves reading old data from an on-chip store, detecting errors with ECC, and updating it, then writing only new data blocks that differ to the on-chip store, with a non-traditional 'dirty bit' marking changed data for efficient off-chip transfer, thereby reducing off-chip bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write-back cache policy is implemented, then processor performance is improved by reducing unnecessary write cycles to main memory, but off-chip bandwidth is wasted when cache lines are written to main memory even when data is identical
Solution Approach 1:
The patent applies preliminary action by comparing new data with old data in the cache line before writing to main memory. The cache controller reads the old data from the cache line, compares it with the new data, and determines whether the data blocks are different before initiating a write operation. This preliminary comparison prevents unnecessary writes of identical data to main memory, reducing off-chip bandwidth consumption while maintaining the write-back cache policy's performance benefits.
2Reliability
If traditional dirty bit implementation is used, then cache controller tracks modified cache lines, but all cache lines are written to main memory regardless of whether data actually changed
Solution Approach 1:
The patent applies segmentation by dividing the cache line into multiple data blocks and implementing separate dirty bits for each data block instead of a single dirty bit for the entire cache line. This allows the cache controller to track which specific data blocks have been modified and only write the changed blocks to main memory, rather than writing the entire cache line regardless of actual data changes.
Solution Approach 2:
The patent applies local quality by making the dirty bit tracking granular at the data block level rather than at the cache line level. Each data block has its own dirty bit that indicates whether that specific block has been modified. This local tracking enables precise control over what data is written to main memory, reducing bandwidth consumption by writing only the necessary changed blocks while maintaining memory system integrity.
3Reliability
If cache lines are written to main memory to maintain consistency, then main memory is kept updated, but bandwidth is consumed even when new data is identical to old data
Solution Approach 1:
The patent applies preliminary action by performing a comparison between new data and old data before writing to main memory. The cache controller reads the old data from the cache line, compares it with the new data to determine if data blocks are different, and only initiates a write operation when actual differences are detected. This preliminary comparison maintains memory consistency by ensuring updated data is written when necessary while reducing data transfer volume by avoiding writes of identical data.
Data Source
AI summary
A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the new data and associated old data bytes of the old data are different. The new data bytes are then written to the on-chip store. When updating an off-chip store, only the new data bytes that are different are written to the off-chip store. In this manner, off-chip bandwidth requirements for a processor may be reduced.