Processor Cache Flush for Low Power State Coherency

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Solution Overview

Problem

In processors, maintaining cache coherency during low power states is challenging, especially when the supply voltage is maintained, as it requires managing memory transactions and clock domains, leading to increased power consumption and design complexity.

Innovation Solution

A processor with a data cache and a control unit that flushes cache blocks to a secondary cache when transitioning to a low power state, inhibiting clocks and writing modified blocks to the secondary cache, thereby maintaining coherency without active clocking of the cache and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If the processor maintains supply voltage during low power state to retain cache state, then cache data is preserved, but cache coherency management complexity and power consumption increase

Engineering Contradiction:

Improvecache data retentionVSAvoidcache coherency management

Core Design Contradiction:

Loss of informationVSDevice complexity

Solution Approach 1:

The processor performs a cache flush operation before transitioning to the low power state, writing all cache data to main memory in advance. This preliminary action ensures that when the processor wakes up, the cache is already coherent with main memory, eliminating the need for complex coherency management during the low power state.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the processor continues clocking the cache during low power state, then cache coherency is maintained, but power consumption increases

Engineering Contradiction:

Improvecache coherencyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The cache clocking function is extracted from the continuous operation and performed only when needed - specifically, the cache is flushed to main memory before entering low power state and reloaded upon waking up. This eliminates the need for continuous clocking during low power state while maintaining coherency.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If the processor is woken up to perform a snoop, then cache coherency is checked, but power consumption increases for wake-up and potential cache miss

Engineering Contradiction:

Improvecache coherency verificationVSAvoidwake-up power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The cache is flushed to main memory before entering low power state, establishing coherency in advance. This preliminary action eliminates the need for snooping operations upon wake-up, as the cache is guaranteed to be coherent with main memory after the flush operation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8171326B2L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down

Publication Date: 2012.05.01 APPLE INC

AI summary

In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.