Processor Cache Hierarchy with Mid-Level Invalidation Mediator
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Solution Overview
Problem
Existing network processors face challenges in efficiently processing and securing network protocol layers from L3 to L7, particularly in managing cache hierarchies to optimize performance and security.
Innovation Solution
A memory subsystem with a three-level cache hierarchy, including L1 instruction and data caches, a mid-level cache, and a low-level cache and controller, which maintains a directory to track instruction and data locations and selectively sends invalidation commands to optimize cache operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-level cache hierarchy (L1, mid-level, and low-level cache) is implemented, then data access performance is improved and communication traffic within the memory subsystem is reduced, but device complexity increases due to the need to manage multiple cache levels and maintain a directory to track instruction and data locations
Solution Approach 1:
The cache hierarchy is segmented into three distinct levels (L1 instruction cache, mid-level instruction cache, and low-level cache) with specialized functions. Each level manages specific portions of the cache hierarchy, allowing independent optimization and reduction of complexity in individual segments while achieving overall performance improvement.
Solution Approach 2:
The mid-level instruction cache acts as an intermediary between the L1 instruction caches and the low-level cache. It receives invalidation commands from the low-level cache and selectively propagates them to L1 caches, reducing the communication burden on the L1 caches while maintaining coherence across the hierarchy.
2Reliability
If the low-level cache sends invalidation commands to the mid-level cache, then data integrity is maintained across multiple processor cores, but communication traffic within the memory subsystem increases
Solution Approach 1:
The system performs partial invalidation actions by selectively sending invalidation commands only when necessary. The low-level cache determines whether an invalidation is needed based on whether the instruction is stored at the mid-level cache, avoiding unnecessary communication while maintaining data integrity.
Solution Approach 2:
The mid-level cache maintains its own state information about stored instructions and autonomously manages invalidation operations. It receives invalidation commands from the low-level cache and selectively propagates them to L1 caches based on its own state, reducing the burden on other components.
3Reliability
If a directory is maintained to track instruction and data locations, then cache coherence is improved, but device complexity and memory subsystem bandwidth requirements increase
Solution Approach 1:
The directory tracking function is extracted and centralized at the low-level cache, which maintains the directory to track instruction and data locations. This centralization simplifies the overall system architecture by concentrating the complexity in one location rather than distributing it across multiple cache levels.
Solution Approach 2:
The low-level cache serves multiple functions: it acts as a cache level, maintains the directory for tracking locations, and manages invalidation operations. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall system complexity while maintaining coherence.
Data Source
AI summary
A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.