Processor Cache Policy Management via Memory Device Context

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Solution Overview

Problem

Conventional cache policies are applied uniformly across all processes, leading to inefficiencies as they are not tailored to specific memory device settings, which can result in suboptimal processor performance for certain types of applications.

Innovation Solution

Determine cache policies based on cache policy information associated with the target memory device accessed during a memory operation, allowing for tailored caching operations that optimize performance for specific memory device settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If uniform cache policies are applied to all processes, then implementation simplicity is maintained, but processor performance deteriorates for certain applications

Engineering Contradiction:
Improvecache policy implementation simplicityVSAvoidprocessor performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies local quality by associating different cache policies with different target memory devices rather than applying a single uniform policy to all memory accesses. Each memory device can have its own optimized cache policy based on its characteristics and the applications that access it, thereby improving processor performance without significantly complicating the overall implementation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamic cache policy selection by determining which target memory device is being accessed and applying the appropriate cache policy associated with that device. This dynamic approach allows the system to adapt cache behavior to different memory devices and applications, improving performance while maintaining reasonable implementation complexity through automated policy selection.

Inventive Principle:
Principle #15Dynamics

2Productivity

If cache policies are tailored to specific memory device settings, then processor performance is improved, but system complexity increases

Engineering Contradiction:
Improveprocessor performanceVSAvoidcache policy management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-establishing associations between target memory devices and their optimized cache policies before runtime. This allows the system to have multiple device-specific policies prepared in advance, enabling performance optimization without requiring complex real-time decision-making or policy generation during execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism (the memory management unit) that automatically determines which target memory device is being accessed and selects the appropriate cache policy. This intermediary handles the complexity of policy management internally, allowing applications to benefit from optimized policies without directly managing the complexity themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If per-page cache policies are used, then basic memory management is simplified, but cache efficiency deteriorates for specific memory device types

Engineering Contradiction:
Improvecache policy structure simplicityVSAvoidcache efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies segmentation by dividing cache policy management into two levels: per-page policies for basic memory management and per-target-memory-device policies for optimization. This segmentation allows the system to maintain the simplicity of conventional per-page policies while adding device-specific optimization layers, thereby improving cache efficiency without completely restructuring the existing policy framework.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7949834B2Method and apparatus for setting cache policies in a processor
Publication Date: 2011.05.24 QUALCOMM INC
  • US7949834B2 patent drawing
  • US7949834B2 patent drawing
  • US7949834B2 patent drawing

AI summary

According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.