Processor Cache Resizing for Low-Power Transition Overhead

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Solution Overview

Problem

Transitioning processor cores and associated caches to low-power modes incurs significant overhead due to cache flushing and initialization, which reduces overall power savings.

Innovation Solution

Adaptive cache resizing based on identified workload characteristics, such as cache victim count and activity levels, to minimize cache size during low-power mode transitions, thereby reducing overhead and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If processor cores and caches are placed in low-power mode during low processing activity, then power consumption is reduced, but transition overhead (cache flushing and initialization) increases

Engineering Contradiction:
Improvepower consumptionVSAvoidtransition overhead
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The cache size is dynamically adjusted based on workload characteristics. The system monitors cache activity metrics (such as cache miss rates, hit rates, or access patterns) and automatically resizes the cache between full size and reduced size. This dynamic adaptation allows the cache to maintain optimal performance during high-activity periods while minimizing power consumption during low-activity periods, thereby reducing both power consumption and transition overhead compared to static low-power mode approaches.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If cache size is reduced during low-power mode, then power consumption and transition overhead are reduced, but performance may be degraded

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system implements a feedback mechanism that continuously monitors cache performance metrics (such as miss rates, hit rates, or access patterns) and uses this information to make intelligent decisions about cache resizing. When performance degradation is detected, the system can prevent resizing or trigger a resize to a larger size, ensuring that performance requirements are met while still achieving power savings when appropriate.

Inventive Principle:
Principle #23Feedback

3Productivity

If full cache size is maintained during low-power mode, then performance is maintained, but power consumption and transition overhead increase

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system changes the operational parameters of the cache by adjusting its size based on workload conditions. During low-power mode with light workloads, the cache is resized to a smaller capacity, reducing the number of cache lines that need to be flushed to memory and reducing initialization overhead. The system monitors workload intensity and cache usage patterns, and only reduces cache size when performance impact is minimal, thereby achieving power savings without significantly compromising performance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12536050B2Cache resizing based on processor workload
Publication Date: 2026.01.27 ADVANCED MICRO DEVICES INC
  • US12536050B2 patent drawing
  • US12536050B2 patent drawing
  • US12536050B2 patent drawing

AI summary

A processor sets the size of a processor cache based on an identified workload executing at the processor. The cache size is set in response to the processor exiting a low-power mode. By setting the size of the cache based on the workload, the processor is able to tailor the size of the cache to the characteristics of a particular workload while also reducing, for at least some workloads, the overhead associated with entering or exiting the low-power mode.