Processor Cache and Scratch Pad Memory Allocation
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Solution Overview
Problem
Current processor architectures face inefficiencies in data access times due to the differences in latency between cache and Scratch Pad Memory (SPM), with cache providing faster access but complex configuration and SPM offering multi-port functionality but higher latency, necessitating a method to optimize memory allocation and processing.
Innovation Solution
A processor architecture that includes a single-port cache and a multi-port SPM, where instructions are allocated based on profiling information and data interference graphs, with latency-based scheduling and timestamp management to optimize data partitioning and processing, allowing for efficient allocation of load and store instructions between the cache and SPM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in cache memory for faster access, then data access speed is improved, but memory configuration complexity increases
Solution Approach 1:
The memory system is segmented into two distinct parts: a single-port cache memory for fast access and a multi-port scratch pad memory for bulk data storage. This segmentation allows each memory type to be optimized for its specific function, reducing overall system complexity while maintaining high access speeds for critical data.
Solution Approach 2:
The processor core acts as an intermediary that intelligently partitions data between the cache and scratch pad memory based on access patterns and timing requirements. This mediator function simplifies the memory configuration by providing a clear division of labor between the two memory types.
2Adaptability or versatility
If SPM is used for multi-port functionality, then memory access parallelism is improved, but data access latency increases
Solution Approach 1:
Different quality levels of memory access are provided for different data: frequently accessed data is stored in the low-latency single-port cache, while less critical data is stored in the multi-port scratch pad memory. This local quality differentiation resolves the contradiction by ensuring that only necessary data suffers from higher latency.
Solution Approach 2:
Data is pre-partitioned and pre-positioned in the appropriate memory (cache or scratch pad) based on predicted access patterns and timing requirements. This preliminary action ensures that when access is needed, the data is already in the optimal location, minimizing actual access latency.
3Productivity
If data is partitioned and allocated between cache and SPM based on profiling information, then memory usage efficiency is improved, but processing complexity increases
Solution Approach 1:
The system uses self-service mechanisms where the processor core automatically performs data partitioning and allocation based on built-in profiling capabilities and data interference graph analysis. This self-service approach improves memory efficiency without requiring external complex control systems.
Solution Approach 2:
The system dynamically changes parameters such as data partitioning ratios, allocation decisions, and scheduling priorities based on profiling information and runtime conditions. These parameter changes enable efficient memory usage while keeping the processing logic adaptable rather than statically complex.
Data Source
AI summary
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.