Processor Carry Registers Feedback for Cryptography Speed
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Solution Overview
Problem
Current computer systems face inefficiencies in performing cryptographic computations, particularly in public-key cryptosystems like RSA and Elliptic Curve Cryptography, due to the compute-intensive nature of modular exponentiation and large integer arithmetic, which require numerous multiplications and additions, leading to performance bottlenecks.
Innovation Solution
The method involves using a feedback mechanism where high-order bits from previous arithmetic operations are fed back to subsequent operations, utilizing extended carry registers to propagate and accumulate results efficiently, enabling faster multi-word multiplications and additions through instructions like umulxc and umulxck, which combine multiply and accumulate operations, reducing the need for explicit carry handling and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional general-purpose processors are used for public-key cryptography, then the system can support standard cryptographic algorithms, but the computation speed is slow due to the compute-intensive nature of modular exponentiation requiring over 1.6 million 64-bit multiplications
Solution Approach 1:
The patent segments large integer multiplication into multiple word-size multiplications with systematic carry propagation. The 1024-bit modular exponentiation is broken down into sequences of smaller multiplications, where each multiplication is further divided into word-size operations. This segmentation allows the computation to be organized into manageable stages that can be executed efficiently in a pipelined manner, improving overall throughput while maintaining correctness through structured carry handling.
Solution Approach 2:
The patent implements preliminary action by pre-computing and storing high-order bits from previous multiplication operations in extended carry registers. These pre-computed values are made available for subsequent operations, eliminating the need to recompute them and reducing latency. The extended carry registers hold intermediate results ready for the next multiplication stage, enabling faster continuation of the cryptographic computation.
2Measurement precision
If the number of arithmetic operations is increased to achieve accurate modular exponentiation, then computation precision is maintained, but the number of instructions increases leading to more data movements and higher complexity
Solution Approach 1:
The patent merges multiplication and addition operations into unified arithmetic structures that can perform both operations within the same hardware pipeline. The extended carry registers are integrated directly into the multiplication units, allowing carry propagation to be combined with the next multiplication operation rather than being separate sequential steps. This merging reduces the total number of independent instructions needed while maintaining computational precision.
Solution Approach 2:
The patent introduces extended carry registers as intermediary structures that hold high-order bits between multiplication operations. These intermediaries facilitate accurate computation by preserving carry information without requiring immediate propagation, allowing the system to maintain precision while reducing the complexity of instruction sequencing. The intermediaries act as buffers that simplify the control logic needed for accurate modular exponentiation.
3Reliability
If carry propagation is performed explicitly in each multiplication operation, then arithmetic accuracy is ensured, but the latency increases due to sequential carry handling
Solution Approach 1:
The patent performs preliminary action by computing and storing high-order bits in extended carry registers during the current multiplication operation, before the next multiplication begins. This pre-computation ensures that when the next multiplication occurs, the carry values are already ready, eliminating sequential wait time. The accuracy is maintained because the carry propagation is systematically performed in advance rather than deferred.
Solution Approach 2:
The patent achieves continuity of useful action by overlapping carry propagation with subsequent multiplication operations. While one multiplication is completing its carry propagation, the next multiplication can begin using pre-computed values from extended carry registers. This continuous pipeline operation eliminates idle time between operations, reducing overall latency while maintaining arithmetic accuracy through systematic carry handling.
Data Source
AI summary
In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.