Processor Secure Cipher Hash Round Logic

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Solution Overview

Problem

Existing cryptographic hash functions are susceptible to denial of service attacks and load imbalance issues due to their susceptibility to 'Zipfs law' or 'Pareto distribution', which can lead to biased resource loading and inefficiencies, particularly in distributed systems.

Innovation Solution

The implementation of secure cipher hash round functionality using instructions and processing logic that perform specific iterations of algorithms like Feistel ciphers (DES, TDES) within a processor, allowing for reversible operations and adaptable key management to thwart attacks, while maintaining efficient pipeline throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional hash functions are used for load balancing, then resource allocation is simplified, but the system becomes vulnerable to denial of service attacks and load imbalance due to Zipf's law

Engineering Contradiction:
Improveresistance to denial of service attacksVSAvoidhash function complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hash function is divided into multiple round functions that can be independently configured. Each round function processes a portion of the hashing operation, allowing the system to use different numbers of rounds for different applications - more rounds for security-critical operations and fewer rounds for performance-critical operations, thus resolving the contradiction between reliability and complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic configuration of hash round functions where the number and type of rounds can be adjusted based on security requirements and performance needs. This allows the system to adaptively balance between security (reliability) and computational overhead (complexity) by selecting appropriate round configurations for different operational contexts

Inventive Principle:
Principle #15Dynamics

2Reliability

If more hash rounds are performed to increase security, then resistance to attacks improves, but processing time and latency increase

Engineering Contradiction:
Improvecryptographic securityVSAvoidhash operation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements partial hashing by allowing selective execution of a subset of round functions rather than requiring complete execution of all rounds. This enables the system to achieve sufficient security with fewer rounds for time-sensitive operations, while maintaining the option to perform complete hashing when security is the primary concern, thus balancing security and latency requirements

Inventive Principle:
Principle #16Partial or excessive action

3Stability of the object's composition

If fixed hash functions are used for consistent hashing, then load distribution stability improves, but adaptability to changing security requirements deteriorates

Engineering Contradiction:
Improveload distribution consistencyVSAvoidsecurity requirement adaptability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal hash computation framework that can perform multiple functions through configurable round selections. The same hash infrastructure supports both consistent hashing applications (where stability is key) and security-critical applications (where adaptability to security requirements is key), allowing a single system to serve multiple purposes by adjusting round configuration rather than requiring separate fixed functions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3031167B1Instruction and logic to provide a secure cipher hash round functionality
Publication Date: 2019.02.06 INTEL CORP
  • EP3031167B1 patent drawingFigure 1A
  • EP3031167B1 patent drawingFigure 1B
  • EP3031167B1 patent drawingFigure 1C

AI summary

Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.