Reconfigurable Processor Circuit with Scalable Arithmetic Core Pairing
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Solution Overview
Problem
Existing computing systems face limitations in processing speed and energy efficiency for mathematically intensive applications such as artificial intelligence, neural networks, digital currencies, and blockchain, with a need for scalable, low-latency, and energy-efficient solutions capable of real-time processing and massive parallel processing.
Innovation Solution
A reconfigurable arithmetic engine with an array of fractal cores, featuring a scalable architecture that includes input reordering queues, a multiplier shifter and combiner network, an accumulator circuit, and control logic, allowing for various operating modes and interconnection networks to optimize hardware for specific applications, enabling efficient processing of streaming data and supporting operations like FFTs and machine learning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for mathematically intensive applications, then general-purpose computing is maintained, but processing speed and energy efficiency deteriorate
Solution Approach 1:
The patent implements dynamically reconfigurable computational cores that can change their operational mode based on the specific computational task. The cores support multiple precision modes (single-precision, half-precision, quarter-precision) and can be reconfigured via control signals to optimize for different mathematical operations, enabling the system to adapt its architecture in real-time for maximum energy efficiency and processing speed
Solution Approach 2:
The system changes operational parameters such as precision level, core activation count, and interconnection network configuration based on computational requirements. The patent uses parameter control mechanisms to adjust the operational state of computational cores and interconnection networks, optimizing the balance between processing speed and energy consumption for different mathematical intensive applications
2Productivity
If computing architecture is optimized for specific applications, then processing efficiency is improved, but adaptability to other applications deteriorates
Solution Approach 1:
The patent designs universal computational cores that can perform multiple mathematical operations including single-precision multiply-accumulate, half-precision operations, quarter-precision operations, and dot product calculations. The same physical hardware infrastructure serves multiple computational purposes through reconfiguration, maintaining high processing efficiency across diverse applications without requiring separate specialized architectures
Solution Approach 2:
The reconfigurable nature of the computational cores allows the system to dynamically adapt its functionality for different applications. Control logic receives operation codes and configures the computational cores accordingly, enabling the same hardware to efficiently handle neural network computations, digital signal processing, encryption, or other mathematically intensive tasks as needed
3Productivity
If number of computational cores is increased for massive parallel processing, then processing capability is improved, but device complexity and heat dissipation worsen
Solution Approach 1:
The patent segments the computational system into modular computational cores that can be activated in different quantities based on processing requirements. Instead of requiring all cores to be simultaneously active and interconnected, the system can activate subsets of cores (e.g., 64, 128, 256, or 512 cores) and use hierarchical interconnection networks that reduce routing complexity by organizing cores into groups with local and global interconnection levels
Solution Approach 2:
The interconnection network uses multi-dimensional routing strategies where cores are organized in hierarchical groups with local interconnections within groups and global interconnections between groups. This dimensional organization reduces the complexity of full mesh interconnection by logarithmic factors while maintaining efficient data flow for parallel processing operations
4Productivity
If reconfigurable architecture is implemented, then energy efficiency and processing speed are improved, but device complexity increases
Solution Approach 1:
The reconfiguration mechanism uses dynamic control signals to change the operational mode of computational cores without requiring physical restructuring. Control logic units receive operation codes and generate appropriate configuration signals that route data through different internal pathways of the same hardware, enabling multiple functions from a single circuit design while maintaining relatively simple physical architecture
Solution Approach 2:
The patent implements universal computational core designs that perform multiple operations (single-precision MAC, half-precision operations, quarter-precision operations, dot products) using the same physical circuitry. This multi-functionality reduces overall device complexity compared to having separate dedicated circuits for each operation type, as the same hardware block can be reconfigured to handle different computational tasks
Data Source
AI summary
A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.