Processor Circuit Shared Memory Parallel Convolution
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Solution Overview
Problem
Deep learning processor circuits face inefficiencies in image reading processing due to multiple cores reading identical images from memory, which increases processing time and reduces efficiency, especially in convolution operations that are prevalent in deep neural networks.
Innovation Solution
A processor circuit configuration with multiple processor cores, individual memories, shared memories, and memory control circuits that allow for efficient data transfer and access between cores, reducing the number of steps required for reading images by utilizing shared memory banks and parallel processing of convolution operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores read identical images from memory independently, then each core can perform convolution operations in parallel, but the processing time increases and efficiency decreases due to redundant memory access
Solution Approach 1:
Multiple processor cores share a common memory structure (shared memory banks) instead of each core having separate individual memory. The memory control circuits coordinate access to the shared memory, allowing multiple cores to read the same image data simultaneously without redundant memory access operations. This merging of memory resources eliminates the time loss while maintaining parallel processing capability.
Solution Approach 2:
The system pre-loads image data into shared memory banks before convolution operations begin. The memory control circuits prepare the data in advance and make it available to multiple processor cores simultaneously. This preliminary action of data preparation and positioning in shared memory eliminates the need for each core to independently access memory during the convolution process, significantly reducing processing time.
2Ease of operation
If each processor core has its own individual memory, then memory access is simple and direct, but data transfer between cores becomes inefficient and requires additional memory control circuits
Solution Approach 1:
The shared memory banks serve multiple functions: they act as both individual memory for each processor core and as a common data transfer medium between cores. The memory control circuits provide multi-functionality by managing both local core access and inter-core data transfer operations. This universal approach eliminates the need for separate data transfer mechanisms while maintaining ease of memory access.
Solution Approach 2:
The shared memory banks act as an intermediary structure between processor cores, replacing the need for direct core-to-core data transfer mechanisms. Instead of complex point-to-point transfer circuits, cores access data through the shared memory, which mediates the data flow. This intermediary approach simplifies the overall system architecture while enabling efficient data sharing between cores.
3Productivity
If multiple memory control circuits are used to manage data transfer between processor cores, then data transfer capability is enhanced, but the device complexity and number of components increase
Solution Approach 1:
Multiple memory control circuits are merged into a coordinated system that manages shared memory banks. Instead of having separate control circuits for each core's individual memory, the system uses a unified memory control structure that handles data transfer between all cores through the shared memory. This merging reduces the total number of control circuits while maintaining enhanced data transfer capability through coordinated access to shared resources.
Data Source
AI summary
A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.