Processor Clock Pulse Removal for Fast Voltage Droop Mitigation
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Solution Overview
Problem
Voltage droop in processors can cause timing failures and reduce power efficiency, with existing solutions being slow to respond to sudden changes in switched capacitance and clock frequency, resulting in significant droop before power controllers can mitigate the issue.
Innovation Solution
A method using a tap sampled delay line to detect voltage droop by measuring changes in clock edge position, allowing for immediate removal of clock pulses to adjust the clock frequency and mitigate droop, with the droop mitigation circuitry blocking or modifying the clock signal to increase impedance and stabilize voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power supply voltage is adjusted to compensate for voltage droop, then the timing failures are prevented, but the response time is too slow to mitigate sudden voltage droop caused by rapid changes in switched capacitance or clock frequency
Solution Approach 1:
The droop detector continuously monitors the supply voltage and detects droop events before they cause timing failures. By detecting the droop early and generating an interrupt signal immediately, the system can take preliminary action to prevent the droop from reaching critical levels, rather than waiting for the droop to occur and then responding slowly
Solution Approach 2:
The system implements a feedback mechanism where the droop detector continuously monitors the supply voltage and feeds back information about voltage droop to the clock control circuit. This closed-loop feedback enables rapid detection and response to voltage droop conditions, allowing the system to adjust the clock frequency in real-time to compensate for the droop and prevent timing failures
2Productivity
If the clock frequency is increased to execute applications faster, then the productivity is improved, but the voltage droop increases due to the inverse relationship between V DD and clock frequency
Solution Approach 1:
The system dynamically adjusts the clock frequency based on real-time voltage conditions. When voltage droop is detected, the clock control circuit automatically reduces the clock frequency to compensate for the voltage drop. This dynamic adjustment allows the processor to operate at high frequencies when voltage is stable while preventing timing failures when voltage droop occurs, thus maintaining both productivity and reliability
Solution Approach 2:
The system changes the clock frequency parameter in response to detected voltage droop. By monitoring the supply voltage and adjusting the clock frequency accordingly, the system maintains the product of voltage and frequency within acceptable bounds, preventing timing failures while maximizing execution speed when conditions permit
3Productivity
If the effective switched capacitance is increased to improve computational intensity, then the processing capability is improved, but the voltage droop increases due to the inverse relationship between V DD and switched capacitance
Solution Approach 1:
The system dynamically monitors the supply voltage and automatically adjusts the clock frequency in response to changes in effective switched capacitance. When computational intensity increases causing voltage droop, the system reduces the clock frequency to compensate, maintaining timing stability while allowing the processor to operate at high computational intensity when voltage conditions permit
Data Source
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AI summary
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider (21) that is configured to receive an output (Fin) of a clock signal generator (4) (e.g. a phase locked loop) and produce an output signal (Fout) in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way, VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.