Processor Clock Frequency Adjustment for Voltage Droop
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Solution Overview
Problem
Processor modules experience errors due to temporary voltage droops, and existing solutions require complex circuitry to adjust clock frequencies, leading to operational errors during replacement.
Innovation Solution
A processor that generates multiple base clock signals with different phases and enable signals to adjust clock frequencies by modifying these enable signals in response to voltage droops, allowing for seamless frequency reduction without suspending operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spare clock signal is generated and used to replace the module clock signal during voltage droop, then the processor can maintain operation during voltage droop, but operational errors can occur during replacement and complex circuitry is required
Solution Approach 1:
The patent dynamically adjusts the frequency of the existing module clock signal in response to detected voltage droop conditions. The clock signal frequency is reduced to a safe operating level when voltage droop is detected, and restored when normal conditions return. This dynamic adjustment eliminates the need for separate spare clock signal generation circuitry while maintaining processor operation during voltage droop events.
Solution Approach 2:
The patent changes the frequency parameter of the module clock signal based on voltage droop detection. When a voltage droop is detected, the clock frequency is reduced to prevent operational errors. This parameter change approach allows the system to adapt to varying voltage conditions without requiring complex additional circuitry for signal replacement.
2Reliability
If the clock frequency is reduced to account for voltage droop, then operational errors are prevented, but processing speed decreases
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time voltage conditions. The frequency is reduced only during voltage droop events and restored to full speed when normal voltage conditions return. This dynamic approach prevents processing speed degradation during normal operation while maintaining reliability during voltage droop conditions.
Solution Approach 2:
The patent implements periodic monitoring of voltage conditions and adjusts clock frequency accordingly. The voltage droop detector continuously monitors supply voltage and triggers frequency adjustment only when droop conditions are detected. This periodic action ensures processing speed is maintained at maximum during normal operation while providing protection during voltage droop events.
Data Source
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AI summary
A processor [100] adjusts frequencies of one or more clock signals [230] in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals [220, 221, 222, 223, 224, 225, 226, 227], each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.