Processor Clock Frequency Control for Wireless Modem Power Management
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Solution Overview
Problem
Existing active power management schemes are limited by the granularity of clock frequency and supply voltage changes, which are not applicable in architectures where these parameters have defined steps, leading to inefficiencies in power consumption, especially in wireless modem applications with varying processing demands.
Innovation Solution
A method and system that dynamically control processor clock frequency and supply voltage by using a two-level control mechanism, allowing for fine-grained adjustments based on execution profiles, with the ability to vary clock frequency and voltage on a slot-by-slot basis, utilizing a phase-locked loop and automatic voltage supply to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock frequency and supply voltage are changed continuously to optimize power consumption, then power efficiency is improved, but this approach is not applicable in architectures where these parameters have defined granularity
Solution Approach 1:
The patent applies parameter changes by transitioning from continuous parameter adjustment to discrete step-based adjustment. The power management system changes clock frequency and supply voltage in discrete steps according to predefined granularity levels, making the system adaptable to architectures with defined parameter steps while still optimizing power consumption within those constraints.
2Productivity
If clock frequency is increased to meet maximum processing demands, then processing speed is improved, but power consumption increases during idle periods
Solution Approach 1:
The patent implements dynamics by making the clock frequency and supply voltage adjustable rather than fixed. The system dynamically transitions between different frequency levels and voltage steps based on actual processing demands, allowing the processor to operate at high speed when needed and at lower power states during idle periods, thus optimizing the trade-off between productivity and energy consumption.
Solution Approach 2:
The patent applies periodic action through the implementation of execution profiles that define periodic patterns of high and low frequency intervals. The system alternates between high-frequency processing intervals and low-frequency idle intervals in a periodic manner, matching the typical workload patterns of wireless modem applications and reducing overall power consumption while maintaining required processing capability.
3Loss of time
If clock frequency changes are made faster to reduce inactivity periods, then power management speed is improved, but switching time must be reduced to less than milliseconds
Solution Approach 1:
The patent applies preliminary action by pre-configuring execution profiles that define the timing and duration of high and low frequency intervals before actual processing occurs. The power management system prepares the frequency transition parameters in advance based on the execution profile, enabling faster switching by reducing the need for real-time calculation and decision-making during critical transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fast and efficient power management with reduced inactivity periods, achieving automatic power management switching in less than milliseconds, thereby minimizing power consumption while maintaining performance in wireless communication systems.
Implementation Method 1
the clock is generated by a high frequency phase-locked- loop (PLL) output divided by a divisor
Data Source
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AI summary
A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application.