Processor Clock Frequency Control for Power Reduction
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Solution Overview
Problem
Industrial network apparatuses face increased power consumption due to high-frequency operational clock signals required for real-time performance, leading to inefficient power usage and potential loss of real-time task processing.
Innovation Solution
A semiconductor device with a processor that measures its use rate and dynamically adjusts the frequency of the operational clock signal based on measured use rates, optimizing power consumption while maintaining real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor operates with a high-frequency operational clock signal to secure real-time performance, then the real-time task processing capability is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The frequency changing unit dynamically modifies the operational clock signal frequency based on the measured processor use rate, allowing the system to adapt between high performance modes (when needed) and low power consumption modes (when idle), thus resolving the contradiction between real-time performance and power consumption
Solution Approach 2:
The patent changes the parameter of clock signal frequency based on the processor's operational state. By measuring the use rate and adjusting the frequency accordingly, the system optimizes the balance between maintaining real-time performance capabilities and reducing power consumption during idle periods, directly addressing the technical contradiction
2Reliability
If the processor executes the idle task synchronized with the operational clock signal, then the real-time performance is maintained, but the power consumption cannot be reduced
Solution Approach 1:
The patent makes the idle task execution dynamic by allowing the clock signal frequency to be adjusted during idle task execution. The frequency changing unit reduces the clock frequency when the processor is executing idle tasks, thereby reducing power consumption while still maintaining the ability to switch to higher frequencies when real-time tasks require it, thus resolving the contradiction between maintaining real-time performance and reducing energy loss
Data Source
AI summary
A semiconductor device capable of reducing power consumption is provided. A semiconductor device having a processor executing a plurality of tasks while switching the tasks in synchronization with a supplied operational clock signal includes: a processor-use-rate measuring unit configured to measure a use rate of the processor during a first term; and a frequency-dividing-value selecting circuit and a frequency dividing circuit configured to change a frequency of the operational clock signal supplied to the processor during a second term later than the first term on the basis of the use rate measured by the processor-use-rate measuring unit.