Processor Clock Frequency Control for Voltage Noise
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Solution Overview
Problem
Current processor technologies, such as Noise Aware Frequency Locked Loop (NAFLL), do not fully address the inefficiencies and noise-related issues on voltage rails due to the execution of different instruction types, leading to sub-optimal performance and power management, especially as processors become smaller and more complex.
Innovation Solution
The implementation of a method to dynamically control the processor clock frequency based on predicted noise characteristics of incoming instructions, allowing for proactive slowdown of the clock frequency before execution of noisy instructions, thereby reducing inefficiencies and improving performance by allowing less noisy instructions to run at faster rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor operates at high clock frequency to improve performance, then productivity increases, but noise on voltage rails increases causing timing errors and circuit failures
Solution Approach 1:
The system dynamically adjusts clock frequency based on the noise characteristics of incoming instructions. The clock frequency is changed from a first frequency to a second frequency in response to detecting instructions with different noise characteristics, allowing the processor to optimize performance while avoiding timing errors caused by excessive noise
Solution Approach 2:
The patent changes the operational parameters of the processor by adjusting clock frequency based on instruction type. Different instruction types (e.g., integer vs. floating point) have different noise characteristics, and the system modifies the clock frequency parameter accordingly to maintain reliable operation at the maximum possible frequency
2Reliability
If the processor slows down to reduce noise and prevent timing errors, then reliability improves, but productivity decreases
Solution Approach 1:
The system applies different clock frequencies to different instruction types based on their specific noise characteristics. Rather than uniformly slowing down the processor, it selectively adjusts frequency only when noisy instructions are detected, maintaining high performance for low-noise instructions while ensuring reliability for high-noise instructions
3Reliability
If conservative clock frequency is used to accommodate all instruction types, then reliability improves, but productivity decreases due to unused performance headroom
Solution Approach 1:
The system transitions from a static, conservative clock frequency approach to a dynamic approach where frequency is adjusted in real-time based on the detected instruction type. This allows the processor to operate at higher frequencies when possible (improving throughput) while maintaining reliability when noisy instructions are executed
Data Source
AI summary
Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.