Processor Clock Frequency Control for Voltage Stability
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Solution Overview
Problem
Electronic devices face instability and potential shutdown due to sudden momentary power loss (SMPL) resets and auto ship modes triggered by battery voltage drops, especially in low temperature environments, which can lead to inconvenient usage and decreased stability.
Innovation Solution
Implementing a control method that dynamically adjusts the clock frequency of the CPU and IP blocks by monitoring battery voltage levels and temperature, using dynamic voltage frequency scaling (DVFS) to maintain voltage above the threshold, thereby preventing SMPL resets and auto ship modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SMPL warning function controls the clock frequency to prevent voltage drop, then the occurrence of SMPL reset is reduced, but the productivity of the electronic device decreases due to limited clock frequency
Solution Approach 1:
The patent implements dynamic clock frequency control that adjusts the clock frequency based on real-time voltage levels. When voltage is high, the clock frequency is maintained at higher levels for optimal productivity. When voltage drops near the threshold, the clock frequency is dynamically reduced to prevent SMPL reset. This dynamic adjustment resolves the contradiction by making the system adaptable to changing voltage conditions rather than using a fixed low frequency.
Solution Approach 2:
The patent changes the clock frequency parameter based on voltage conditions. The control unit monitors voltage levels and adjusts the clock frequency parameter accordingly - maintaining higher frequencies when voltage is sufficient and reducing the frequency when voltage approaches the threshold. This parameter change strategy allows the system to optimize productivity when possible while preventing SMPL reset when necessary.
2Reliability
If the clock frequency is reduced to prevent voltage drop, then the battery voltage is maintained above threshold, but the usage stability decreases due to frequent adjustments
Solution Approach 1:
The patent implements preliminary action by predicting future voltage levels based on current trends and proactively adjusting the clock frequency before voltage actually drops to the threshold. The control unit analyzes voltage trends and anticipates potential drops, making preventive adjustments to clock frequency. This avoids the instability caused by reactive adjustments after voltage already dropped, thereby improving usage stability while maintaining battery voltage above threshold.
Solution Approach 2:
The patent uses feedback mechanisms where the control unit continuously monitors voltage levels and adjusts clock frequency based on this feedback. The system learns from voltage patterns and adjusts its control strategy accordingly, smoothing out frequent adjustments and improving usage stability over time while maintaining the primary goal of keeping voltage above the SMPL reset threshold.
3Reliability
If the SMPL warning function is used in low temperature environments, then the auto ship mode is prevented, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent implements a universal control unit that handles multiple functions: normal voltage monitoring, SMPL reset prevention, auto ship mode prevention, and temperature-aware clock frequency control. By making the control unit multi-functional rather than adding separate dedicated circuits for each function, the patent prevents auto ship mode in low temperature environments without significantly increasing device complexity. The same control infrastructure serves multiple protective functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the occurrence of SMPL resets and auto ship modes, enhancing the stability and usability of electronic devices by maintaining battery voltage levels above the threshold, even in low temperature conditions.
Implementation Method 1
using dynamic voltage frequency scaling (DVFS) to maintain voltage above the threshold, thereby preventing SMPL resets and auto ship modes
Data Source
AI summary
An electronic device includes a processor including a central processing unit (CPU) and a plurality of intellectual property (IP) blocks and a memory operationally connected with the processor. The memory stores one or more instructions, when executed, causing the processor to obtain a first voltage level of the electronic device, decrease a clock frequency of a first clock, which is a clock signal supplied to the CPU, when the obtained first voltage level is less than or equal to a specified first threshold voltage, and decrease at least one maximum clock frequency selected from a plurality of maximum clock frequencies, which is set in the CPU and the plurality of IP blocks, when the obtained first voltage level is less than or equal to the first threshold voltage after a first time elapses.