Processor Clock Frequency Control via Load Monitoring
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Solution Overview
Problem
Existing methods for reducing energy consumption in digital signal processors and micro-controllers, such as reducing clock frequency or stopping the clock signal, lead to inefficient energy usage and potential cross-coupling issues with other components, as they do not accurately adapt to the instantaneous computing capacity requirements.
Innovation Solution
A method and device that dynamically set the clock frequency based on processor load values, using input and output buffer memories to ensure real-time processing and adapt computing capacity to actual requirements, minimizing inactive phases and energy uptake.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock frequency is reduced to adapt computing capacity to worst-case requirements, then energy consumption is reduced, but computing efficiency deteriorates because algorithms require far less than worst-case capacity on average
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable and adaptive rather than fixed. The control unit dynamically changes the clock frequency based on real-time processor load values, allowing the system to transition between low frequency (when idle) and high frequency (when needed), thereby optimizing the balance between energy consumption and computing efficiency.
Solution Approach 2:
The patent changes the parameter of clock frequency based on measured processor load values. The control unit monitors the processor load and adjusts the clock frequency accordingly, transforming the static frequency parameter into a dynamic one that adapts to actual computational demands, thus reducing energy waste while maintaining efficiency.
2Use of energy by moving object
If the clock signal is stopped when all tasks are processed, then energy consumption is reduced, but current peaks occur during activation/deactivation that can cause cross-coupling with other components
Solution Approach 1:
Instead of completely stopping the clock signal, the system dynamically adjusts it to match the processor's operational state. When the processor is idle, the clock frequency is reduced to a low level rather than being completely stopped, which prevents abrupt current peaks and associated cross-coupling effects with other components like ADCs or DACs.
Solution Approach 2:
The patent maintains continuous clock signal generation at an adjusted frequency rather than complete stoppage. This continuous operation at reduced frequency avoids the abrupt on/off current transitions that cause harmful peaks, while still achieving energy savings compared to continuous high-frequency operation.
3Use of energy by moving object
If the clock frequency is set to match instantaneous computing capacity requirements, then energy consumption is significantly reduced, but the system complexity increases due to load monitoring and frequency adjustment mechanisms
Solution Approach 1:
The processor essentially monitors its own load and triggers appropriate clock frequency adjustments through an integrated control unit. This self-service mechanism allows the system to automatically adapt to its own computational demands without requiring external complex monitoring systems, thereby limiting the increase in overall system complexity.
Solution Approach 2:
The system implements feedback by continuously monitoring the processor load value and using this information to adjust the clock frequency. This closed-loop control mechanism, while adding some complexity, enables significant energy savings by ensuring the clock frequency always matches the actual computational requirements.
Data Source
AI summary
In order to set the clock frequency of a processor it is proposed that a processor load value be determined, representing a measure for the instructions carried out by the processor during a unit of time, and the clock frequency of a clock signal of the processor be set depending on the processor load value determined. To this end, an appropriately configured device has a clock signal source which provides the clock signal at a clock frequency which can be set depending on a clock frequency control signal. The processor load value is preferably determined by a time counter module which detects lengths of time during which the processor is in an inactive state. A control unit computes the value to which the clock frequency is set depending on a relative proportion of time TI during which the processor is in the inactive state. An input buffer memory co-operates with a data input of the processor and an output buffer memory co-operates with a data output of the processor, and allowance is preferably made for the degree to which they are full in order to adapt the clock frequency.