Processor Clock Synchronization Using PLL Feedback for Lockstep
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Synchronizing clock signals between multiple processors in lockstep operation is challenging due to differences in signal line lengths, material imperfections, temperature variations, and clock drift, especially at high frequencies and when processors are physically separated, leading to difficulties in maintaining alignment.
Innovation Solution
A circuit and method using a phase comparator and phase-locked loop to determine and adjust phase differences between processors, allowing them to synchronize and maintain lockstep operation by adjusting clock signals, even when driven by separate clock sources, and utilizing internal or external phase-locked loop circuitry for synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processors are physically separated to improve system architecture flexibility, then adaptability is improved, but clock synchronization precision deteriorates due to compounded silicon and board delays
Solution Approach 1:
The patent employs a phase comparator that continuously monitors the phase difference between clock signals from separate processors and feeds this information back to adjust the timing. This closed-loop feedback mechanism compensates for propagation delays caused by physical separation, maintaining synchronization precision despite increased architectural flexibility.
Solution Approach 2:
The invention introduces a timing adjustment circuit as an intermediary component that mediates between the physically separated processors. This intermediary measures the phase difference and applies corrective timing adjustments, effectively bridging the synchronization gap created by physical separation.
2Productivity
If clock signal frequency is increased to improve processing speed, then productivity is improved, but clock drift increases making synchronization more difficult to maintain
Solution Approach 1:
The phase-locked loop continuously monitors phase differences between high-frequency clock signals and applies real-time feedback correction. This feedback mechanism counteracts the increased clock drift that occurs at higher frequencies, maintaining synchronization stability despite improved processing speed.
Solution Approach 2:
The invention implements dynamic timing adjustment that adapts to changing conditions. The timing adjustment circuit continuously modifies timing parameters in response to measured phase differences, enabling the system to maintain synchronization even as clock drift varies with temperature, frequency, and other environmental factors.
3Device complexity
If separate clock sources are used to improve system modularity, then device complexity is reduced, but synchronization difficulty increases due to initial alignment and drift issues
Solution Approach 1:
The patent implements a self-synchronizing mechanism where the system automatically aligns and maintains synchronization between separate clock sources without external intervention. The phase comparator and timing adjustment circuit work together to autonomously correct phase differences and compensate for drift, making the system easy to operate despite using modular separate clock sources.
Solution Approach 2:
The continuous feedback loop monitors and corrects synchronization errors between separate clock sources, eliminating the need for manual alignment. The system automatically detects and compensates for phase differences and drift, maintaining synchronization while preserving the benefits of modular architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively synchronizes processors, maintaining lockstep operation by continuously monitoring and adjusting clock signals to ensure phase alignment, even at high frequencies and across physical separations, thereby enhancing system reliability and stability.
Implementation Method 1
A first phase-locked loop circuit having an input coupled to a clock source generator, an output coupled to a clock input of the first processor, and a control input coupled to an output of the phase comparator
Data Source
AI summary
A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.