Processor Clock Frequency Control via Noise Shaper

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Solution Overview

Problem

Existing methods for controlling processor clock frequency are complex and lack precise control over idle times, leading to undesirable active and inactive cycles, which can cause disturbances and inefficiencies in processor performance.

Innovation Solution

A method using a noise shaper to generate a processor clock frequency by combining a reference signal with a control value-based second signal, allowing for adaptive frequency adjustment to balance idle times and processor load.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a high clock frequency is used to reduce processor idle time, then productivity improves, but energy consumption increases

Engineering Contradiction:
Improveprocessor productivityVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamic frequency adjustment by continuously monitoring processor utilization and adapting the clock frequency in real-time. The frequency is increased when utilization is high to maximize productivity, and decreased when utilization is low to reduce energy consumption, creating a dynamic balance between performance and power efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter based on processor utilization measurements. By adjusting this critical parameter dynamically, the system optimizes the trade-off between productivity (higher frequency) and energy consumption (lower frequency) according to actual workload conditions

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a fixed clock frequency is used, then device complexity is reduced, but adaptability to varying workload deteriorates

Engineering Contradiction:
Improvecontrol mechanism complexityVSAvoidworkload adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements a feedback mechanism where processor utilization is continuously measured and fed back to the frequency control logic. This closed-loop system automatically adjusts the clock frequency based on actual workload conditions, providing high adaptability without requiring complex manual control mechanisms

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The frequency control system operates autonomously by self-monitoring processor utilization and self-adjusting the clock frequency accordingly. This self-service approach eliminates the need for external complex control mechanisms while maintaining high adaptability to varying workload conditions

Inventive Principle:
Principle #25Self-service

3Device complexity

If coarse frequency control is used, then device complexity is reduced, but measurement precision of idle time control deteriorates

Engineering Contradiction:
Improvefrequency control complexityVSAvoididle time control precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent uses dynamic frequency adjustment with fine-grained control steps rather than coarse fixed increments. This allows precise control of idle time by making small, incremental frequency changes that can accurately match the desired idle time targets, improving measurement precision without excessive complexity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9360913B2Method of providing a clock frequency for a processor
Publication Date: 2016.06.07 NXP BV
  • US9360913B2 patent drawing
  • US9360913B2 patent drawing
  • US9360913B2 patent drawing

AI summary

A method of providing a clock frequency to a processor is described. The method in accordance with the invention comprises the step of providing at least one reference signal and the step of determining a control value which relates to a desired first frequency. A second signal that relates to the control value is then used in a subsequent step as an input signal for a noise shaper. Then, a first signal which has the first frequency is generated by combining the output of the noise shaper with one of the at least one reference signals. The first signal is used as a clock frequency of the processor. In a preferred embodiment, one reference signal with a fixed reference frequency is provided. The reference signal is gated or enabled and hold by the output signal provided by a 1-bit noise shaper, whereby the first frequency is generated which is then used as processor clock frequency. The method in accordance with the invention is particularly advantageous as it allows for the control of the processor's clock frequency via the second signal that is fed into the noise shaper.