Processor Clock Throttling for Overcurrent Shutdown Prevention

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Solution Overview

Problem

Existing overcurrent protection (OCP) and sudden momentary power loss (SMPL) reset functions in electronic devices can inadvertently turn off the device during operation, causing inconvenience and reducing usability.

Innovation Solution

An electronic device with a charging circuit and processor that includes a first pin to output an overcurrent warning signal, reducing clock frequencies, display luminance, or charging current when a threshold current is reached, thereby preventing unnecessary power-offs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If overcurrent protection function blocks power supply when current exceeds threshold, then circuit and battery are protected, but electronic device is turned off during operation causing inconvenience

Engineering Contradiction:
Improvecircuit protectionVSAvoiddevice usability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The charging circuit outputs an overcurrent warning signal before the processor executes overcurrent protection that would turn off the device. This preliminary warning allows the processor to take preventive actions (reducing clock frequencies, reducing display luminance, reducing charging current) to avoid the harmful power-off effect while still protecting against actual overcurrent damage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the charging circuit monitors current and provides real-time overcurrent warning signals to the processor. The processor continuously adjusts operational parameters (clock frequencies, display luminance, charging current) based on this feedback to maintain current below the protection threshold while preserving device operation.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If processor reduces clock frequency and display luminance in response to overcurrent warning, then device operation is maintained, but processing speed and display quality are reduced

Engineering Contradiction:
Improvedevice continuityVSAvoidprocessing speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The processor dynamically adjusts clock frequencies and display luminance based on real-time overcurrent warning signals rather than maintaining fixed settings. This dynamic adaptation allows the system to optimize performance within safe current limits, reducing parameters only when necessary to prevent overcurrent protection activation.

Inventive Principle:
Principle #15Dynamics

3Reliability

If SMPL reset function turns off device when battery voltage is low, then battery is protected from damage, but device operation is interrupted causing user inconvenience

Engineering Contradiction:
Improvebattery protectionVSAvoiddevice operation time
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The charging circuit provides preliminary overcurrent warning signals before battery voltage drops to the SMPL reset threshold. This allows the processor to take preventive actions (reducing power consumption) before the harmful power-off effect occurs, extending device operation while still protecting the battery.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12541242B2Electronic device and method for controlling electronic device
Publication Date: 2026.02.03 SAMSUNG ELECTRONICS CO LTD
  • US12541242B2 patent drawing
  • US12541242B2 patent drawing
  • US12541242B2 patent drawing

AI summary

An electronic device is provided. The electronic device includes a battery, a power management module, a charging circuit, and a processor including a central processing unit (CPU) and a plurality of intellectual property (IP) blocks. The charging circuit is connected to the processor and includes a first pin to output a first overcurrent warning signal. The power management module is connected to the processor and includes a second pin to output a reset warning signal. The processor includes a first general purpose input output (GPIO) pin to receive the first overcurrent warning signal, and is configured to reduce at least one clock frequency among a plurality of clock frequencies set to each of the CPU and the plurality of IP blocks, or reduce at least one operation clock frequency of components inside the electronic device when the first overcurrent warning signal is received through the first GPIO pin.