Processor Base Clock Configuration for Thermal Design Power Compliance
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Solution Overview
Problem
Manufacturers restrict processors to operate at a fixed base clock frequency to prevent thermal design power violations, limiting end users' ability to adjust this frequency for different usage scenarios, which hinders cloud service providers from pricing services accurately based on higher clock speeds.
Innovation Solution
End users are provided with the option to set the base clock frequency above or below the manufacturer's assigned value based on usage parameters such as core count, thermal design power, and reliability, using a user interface or application to determine a target frequency, and a power management circuit to adjust core operations accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the manufacturer assigns a fixed base clock frequency to the processor, then the processor can operate reliably within thermal design power limits, but the end user cannot adjust the frequency for different usage scenarios
Solution Approach 1:
The patent implements dynamic base clock frequency adjustment by allowing the end user to modify the base clock frequency value stored in a control register. The power management circuit continuously monitors usage parameters (such as workload, temperature, and power consumption) and dynamically adjusts the base clock frequency within safe operational limits, transforming the static frequency assignment into a dynamic, adaptive parameter that responds to real-time conditions.
Solution Approach 2:
The patent changes the physical parameter of base clock frequency from a fixed manufacturer-assigned value to a user-adjustable parameter. The end user can specify a desired base clock frequency, and the system modifies this parameter while maintaining thermal design power compliance through coordinated adjustment of other operational parameters by the power management circuit.
2Speed
If the processor operates at a higher base clock frequency, then cloud service providers can offer faster processing speeds, but the processor may violate thermal design power requirements
Solution Approach 1:
The patent implements a feedback mechanism where the power management circuit continuously monitors the processor's power consumption, temperature, and workload. When the processor operates at an elevated base clock frequency, the feedback system detects approaching thermal limits and automatically adjusts operational parameters to maintain compliance, enabling sustained high-speed operation within safe thermal boundaries.
Solution Approach 2:
The power management circuit autonomously manages thermal design power compliance by self-adjusting operational parameters in response to monitored conditions. The system performs self-service thermal management without external intervention, allowing the processor to operate at higher frequencies while the power management circuit independently ensures thermal limits are not exceeded.
3Measurement precision
If the manufacturer marks the processor with a specific base clock frequency value, then the processor has a guaranteed performance level, but the end user is restricted from optimizing for specific usage scenarios
Solution Approach 1:
The patent segments the base clock frequency configuration into two parts: a manufacturer-guaranteed minimum value that ensures baseline performance, and a user-adjustable component that allows optimization for specific usage scenarios. The power management circuit maintains the guarantee by ensuring the operational frequency never falls below the marked value under normal conditions, while permitting user-specified adjustments above this baseline.
Data Source
AI summary
A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.