Processor Clock Switching for Supply Voltage Drop Control
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Solution Overview
Problem
The rapid change in load current causes significant voltage drops in processor supply voltage due to parasitic impedance, leading to operational issues, which existing methods attempt to address by increasing decoupling capacitors, supply voltage, or reducing operating frequency, each with drawbacks such as increased manufacturing cost, power consumption, or performance loss.
Innovation Solution
A processor with a detection circuit that real-time monitors supply voltage and selects from multiple clock signals to adjust operating frequency, ensuring optimal performance without excessive frequency changes or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply voltage of the processor is increased to provide sufficient voltage drop buffer, then the processor can maintain stable operation under load changes, but the power consumption of the chip increases
Solution Approach 1:
The patent implements dynamic frequency adjustment by switching between multiple clock signal generation circuits with different frequencies based on real-time voltage detection. The operating frequency is dynamically adapted to match the actual supply voltage level, allowing the processor to maintain stable operation at lower voltages rather than using a fixed high voltage buffer.
Solution Approach 2:
The patent changes the operating frequency parameter in response to voltage variations. By detecting the supply voltage level and adjusting the clock frequency accordingly, the system optimizes the voltage-frequency relationship, enabling stable operation at lower voltages while maintaining performance when voltage is sufficient.
2Reliability
If the operating frequency of the processor is reduced to avoid voltage drop issues, then the processor can operate stably under varying loads, but the performance of the processor deteriorates
Solution Approach 1:
The patent implements dynamic frequency adjustment by switching between multiple clock signal generation circuits with different frequencies based on real-time voltage detection. The operating frequency is dynamically adapted to match the actual supply voltage level, allowing the processor to maintain stable operation at lower voltages rather than using a fixed high voltage buffer.
Solution Approach 2:
The patent changes the operating frequency parameter in response to voltage variations. By detecting the supply voltage level and adjusting the clock frequency accordingly, the system optimizes the voltage-frequency relationship, enabling stable operation at lower voltages while maintaining performance when voltage is sufficient.
3Reliability
If the area of the decoupling capacitor inside the chip is increased to prevent voltage drop, then the processor can maintain stable voltage under rapid load changes, but the manufacturing cost of the chip increases
Solution Approach 1:
The patent replaces the passive electrical approach (increasing decoupling capacitor area) with an active control system consisting of a voltage detection circuit and a multiplexer that switches between multiple clock signal generation circuits. This control-based approach achieves voltage stability without requiring additional physical capacitor area, thereby reducing manufacturing cost.
Data Source
AI summary
The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.