Processor Cluster DVFS for Localized Power Control
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Solution Overview
Problem
Existing power management systems for SoC-based electronic devices lack efficient and flexible mechanisms to manage power consumption and performance across multiple processor clusters, leading to performance degradation due to parasitic effects and electrical noise.
Innovation Solution
Implementing a power management processor within each processor cluster to control voltage and frequency scaling independently, coupled with a system controller for system-level power allocation, enabling dynamic power management at both firmware and system levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a centralized power management system is used for SoC-based electronic devices, then power distribution can be controlled globally, but parasitic effects and electrical noise cause performance degradation
Solution Approach 1:
The patent divides the centralized power management system into distributed power management processors located within each processor cluster. Each cluster has its own power management processor that independently controls power states of processors within that cluster, reducing the impact of parasitic effects and electrical noise by localizing power management functions and minimizing long conductive wire paths.
2Productivity
If processor clusters operate at high performance states, then computational capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) where each power management processor dynamically adjusts the operating voltage and frequency of processors within its cluster based on real-time performance requirements and power constraints. This allows the system to optimize the balance between computational capability and power consumption by transitioning processors between different performance states as needed.
Solution Approach 2:
The patent changes operational parameters (voltage and frequency) of processors dynamically based on workload demands. The power management processor monitors performance state requirements and adjusts voltage and frequency parameters to achieve the necessary computational capability while minimizing power consumption, allowing processors to operate at high performance states only when required.
3Adaptability or versatility
If independent power management is implemented at each processor cluster, then power management flexibility is improved, but system complexity increases
Solution Approach 1:
The patent segments power management functions into distributed power management processors within each cluster, providing local autonomy and flexibility. Each power management processor independently manages its cluster, improving adaptability to local conditions while the modular architecture manages overall system complexity through standardized interfaces and hierarchical control.
Data Source
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AI summary
An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.