Processor Cluster Power Rail Configuration for Leakage Reduction
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Solution Overview
Problem
In multi-core processors, idle cores continue to consume power due to leakage currents, and the use of power switches to reduce this consumption leads to area congestion and a drop in supply voltage, resulting in reduced performance.
Innovation Solution
A processor cluster configuration where a first processor core is directly coupled to a power rail, and a second processor core is coupled through power switches, with a scheduler optimizing task assignment to balance power consumption and performance. The second processor core is decoupled from the power rail during idle states to reduce power consumption, while the first processor core maintains full power to maximize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power switches are used to cut off power to idle cores, then power consumption is reduced, but area is occupied and metal layer congestion is caused
Solution Approach 1:
The patent merges the power switching control for multiple cores into a single shared power switch located in the power delivery network, rather than having separate power switches for each core. This consolidation reduces the total area occupied by power switches and eliminates metal layer congestion while still enabling independent power control of individual cores during idle states.
2Loss of energy
If power switches are used to reduce leakage power, then power consumption is reduced, but supply voltage drops by approximately three percent, causing reduced performance
Solution Approach 1:
The patent introduces a power rail as an intermediary element between the power source and the processor cores. The shared power switch controls power delivery to the power rail, which then distributes power to multiple cores. This intermediary approach allows for effective power control during idle states while maintaining stable voltage levels and avoiding the performance degradation caused by direct power switching at the core level.
3Productivity
If a core is kept active to maintain performance, then performance is maximized, but power is consumed due to leakage currents during idle states
Solution Approach 1:
The patent implements dynamic power management by enabling the system to switch between different operational states based on workload requirements. During active states, cores receive full power for maximum performance. During idle states, the shared power switch dynamically cuts off power to individual cores while maintaining their operational readiness, thus eliminating leakage power consumption without permanently degrading performance capabilities.
Data Source
AI summary
A processor cluster includes a first processor core electrically coupled directly to a power rail and a second processor core coupled to the power rail through power switches. The first processor core consumes power due to leakage currents during idle states. The second processor core is electrically decoupled from the power rail during idle states by the power switches, but the power switches cause a performance degradation. A scheduler assigns tasks to the first processor core rather than the second processor core to maximize performance and minimize power consumption due to leakage currents. Some tasks may indicate that they can be executed on a lower-performance core type, which may be the core type of the second processor core, but those tasks may be assigned to the first processor core while the second processor core is turned off.