Processor Code Patching Device Using Address Matching
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Solution Overview
Problem
Microprocessors with read-only memory face challenges in updating instruction sets to correct defects, as the ROM is frozen and cannot be changed post-manufacture, necessitating a method to patch instruction code and data without modifying the processor or impacting performance.
Innovation Solution
A patching device that uses a comparator to select between ROM and patch data based on address matching, allowing dynamic patching of instructions and data in real-time without requiring processor modifications, utilizing external RAM for patch storage and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If read-only memory is used to store instruction codes, then the memory is physically compact and cost-effective, but the instruction set cannot be updated after manufacture
Solution Approach 1:
The memory system is segmented into two distinct parts: a first memory (ROM) for storing original instruction codes and a second memory (RAM) for storing patch data. This segmentation allows the system to maintain the manufacturing advantages of ROM while adding the flexibility of RAM for updates, resolving the contradiction between manufacturing cost-effectiveness and adaptability.
Solution Approach 2:
A patching device acts as an intermediary between the processor and the memory systems. It intercepts memory access requests, compares addresses, and selectively routes access to either the original ROM or the patched RAM, enabling instruction updates without modifying the processor or sacrificing manufacturing advantages.
2Adaptability or versatility
If a patching mechanism is added to enable instruction updates, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patching functionality is extracted as a separate, standalone device rather than being integrated into the processor core. This externalization contains the complexity in a dedicated module, allowing the processor to remain simple while gaining update capability through the independent patching device.
Solution Approach 2:
The patching device is designed with universal components that can handle multiple patching scenarios. The comparator can compare against multiple stored addresses, and the control unit can route to different memory locations, allowing a single device structure to provide versatile patching capabilities without proportional increases in complexity.
3Adaptability or versatility
If patch data is stored in a separate second memory, then instruction updates become possible, but memory overhead increases
Solution Approach 1:
The system dynamically manages memory usage by allowing the second memory (RAM) to serve dual purposes: storing patch data when updates are needed and serving as regular working memory when not needed. This dynamic allocation optimizes memory resource utilization and reduces overall memory overhead.
Solution Approach 2:
Patch data in the second memory can be discarded after successful application to the first memory, and the same memory space can be recovered and reused for other purposes. This approach minimizes permanent memory overhead while maintaining full patching capability when needed.
Data Source
AI summary
A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.