Processor Coherency Error Logging Mechanism
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Solution Overview
Problem
Current processor architectures face challenges in identifying and locating coherency errors due to the lack of additional information provided by existing coherency error detection mechanisms, making it a highly manual and time-intensive process to determine the cause and location of such errors.
Innovation Solution
A coherency error detection and reporting mechanism that logs information including the address, requestor, command, response, scope, and error type when a coherency error is detected, allowing for more detailed analysis and quicker identification of the error's cause and location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a coherency error detection mechanism sets a bit to report when a coherency error occurs, then the error detection capability is improved, but the ability to identify where and why the error occurred remains insufficient, making the analysis process highly manual
Solution Approach 1:
The patent applies preliminary action by capturing and storing command information (including address, requestor, command type, and response) at the moment a coherency error is detected. This pre-capture of diagnostic data eliminates the need for manual tracing through processor logs later, directly resolving the information loss problem while maintaining reliable error detection
Solution Approach 2:
The patent introduces an intermediary logging mechanism that sits between the coherency error detection logic and the system error handler. This intermediary captures detailed command information and presents it in a structured format to analysts, bridging the gap between simple error detection and comprehensive error diagnosis
2Device complexity
If only a bit is set to indicate a coherency error occurred, then the error reporting mechanism remains simple, but the time required to manually analyze processor logs to determine the cause and location of errors is excessive
Solution Approach 1:
The system performs preliminary capture of all relevant command information (address, requestor, command, response, scope) at the moment of error detection. This pre-packaging of diagnostic data eliminates time-consuming manual log analysis while keeping the error reporting mechanism itself relatively simple through the use of existing processor logging infrastructure
Solution Approach 2:
The patent creates a copy of the relevant command information and stores it in a dedicated error log structure. This copy contains all necessary diagnostic data (address, requestor, command type, response, scope) without requiring analysts to search through original processor logs, significantly reducing diagnosis time while maintaining simple error reporting
Data Source
AI summary
A coherency error detection and reporting mechanism monitors for coherency errors in a processor and between processors. When a requestor broadcasts a memory address in a command and a coherency error is detected, information regarding the command that caused the coherency error is logged, and the coherency error is reported a system error handler. The information logged for the coherency error may include the address of the coherency error, the requestor, the command, the response to the command, the scope of the coherency error, the error type, etc. Logging information relating to the coherency error provides more information to a person analyzing the processor for failures to more easily track down the cause of coherency errors.