Processor Command Encryption Register for Buffer Overflow Defense
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Solution Overview
Problem
Current methods to protect digital processors from Buffer Overflow Attacks (BOAs) are inadequate, as they rely on logical separation of memory blocks and have not entirely eliminated the risk of malicious code overwriting executable instructions, necessitating a more robust solution.
Innovation Solution
Incorporating a digital processor design with a Command Encryption Register (CER) and bit modification circuits that randomly modify instruction bits before storage, using a Seed Value for encryption and decryption, ensuring that malicious code executed results in chaotic behavior and prevents processor control, combined with multiple encryption/decryption algorithms and a Cache system to enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logical separation of memory blocks is used to protect against buffer overflow attacks, then processor security is improved, but the protection is inadequate and malicious code can still overwrite executable instructions
Solution Approach 1:
The patent applies parameter changes by encrypting instruction bits using a seed value stored in a command encryption register. The encryption modifies the binary representation of instructions, transforming them into an unreadable format that prevents malicious code from overwriting executable instructions through buffer overflow attacks. The encrypted instructions are then decrypted and executed normally, maintaining processor security while allowing legitimate code execution.
Solution Approach 2:
The patent introduces an intermediary encryption/decryption mechanism between instruction storage and execution. The command encryption register and associated logic act as a mediator that transforms instructions into encrypted form for storage and back to original form for execution. This intermediary layer blocks direct access to instruction memory by malicious code, resolving the contradiction between security and code executability.
2Object-affected harmful factors
If instruction bits are randomly modified using encryption before storage, then buffer overflow attack resistance is improved, but processor operation complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-storing a seed value in the command encryption register before instruction encryption occurs. This pre-configured seed value enables the encryption logic to systematically transform instructions without requiring complex real-time key generation or management during processor operation. The preliminary setup simplifies the overall encryption process while maintaining strong buffer overflow resistance.
Solution Approach 2:
The patent uses parameter changes by applying a deterministic encryption function that transforms instruction bits based on the seed value. This systematic transformation approach maintains processor operation simplicity while achieving strong buffer overflow attack resistance, as the same seed value consistently produces the same encryption pattern, allowing for efficient decryption and execution.
3Reliability
If encryption and decryption circuits are added to the processor, then security against malicious code is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies segmentation by separating the encryption/decryption functionality into a dedicated command encryption register and associated logic circuitry, distinct from the main instruction execution pipeline. This modular segmentation allows the security features to be added without fundamentally redesigning the entire processor, reducing manufacturing complexity while maintaining strong security against malicious code.
Solution Approach 2:
The patent applies universality by designing the command encryption register to serve multiple functions: storing the seed value, controlling the encryption process, and enabling/disabling encryption based on operational mode. This multi-functionality reduces the number of separate components needed, thereby reducing device complexity and manufacturing difficulty while maintaining comprehensive security protection.
Data Source
AI summary
A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.