Processor Communication Method Reducing Time Delays
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Solution Overview
Problem
Existing processor communication methods experience significant time delays due to the need for bidirectional acknowledges and multiple interrupt signals, which hinder efficient data transmission between processors in electronic devices.
Innovation Solution
A processor communication method that involves transmitting a master interrupt signal upon detecting a downlink packet, receiving a slave acknowledge signal, and then transmitting the packet, followed by a reset master interrupt signal upon completion, eliminating the need for secondary confirmations via slave interrupt and master acknowledge signals, and allowing for batch data transmission when the packet volume exceeds a threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bidirectional acknowledges and multiple interrupt signals are used for processor communication, then data transmission reliability is improved, but communication time delay increases
Solution Approach 1:
The patent extracts and eliminates redundant signal exchange steps from the communication protocol. Specifically, it removes the secondary confirmation signals (slave interrupt and master acknowledge) while retaining the essential master interrupt and slave acknowledge signals, thereby reducing communication delay while preserving necessary reliability
Solution Approach 2:
The patent implements preliminary data buffering and processing before actual data transmission. The master processor prepares data in advance and uses interrupt signals to trigger transmission only when ready, reducing waiting time and improving overall communication efficiency without sacrificing reliability
2Reliability
If multiple interrupt signals and secondary confirmations are implemented, then communication reliability is improved, but device complexity increases
Solution Approach 1:
The patent simplifies the communication protocol by extracting and removing redundant signal types. It retains only the essential master interrupt signal and slave acknowledge signal, eliminating the slave interrupt and master acknowledge signals, thereby reducing protocol complexity while maintaining core reliability functions
Solution Approach 2:
The patent merges multiple communication functions into fewer signal types. The master interrupt signal serves both to initiate transmission and to indicate data readiness, while the slave acknowledge signal confirms both receipt and processing status, reducing the total number of distinct signal types required
3Manufacturing precision
If individual packet transmission with multiple confirmations is used, then data accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent implements preliminary data buffering where the master processor prepares multiple data packets in advance before transmission is needed. This allows the system to maintain high data accuracy through proper protocol handling while improving processing speed by having data ready for immediate transmission
Solution Approach 2:
The patent removes redundant confirmation steps from the individual packet transmission process. By eliminating secondary confirmations while retaining the essential acknowledge signal, it maintains data transmission accuracy through the necessary confirmation mechanism while speeding up the overall transmission process
Data Source
AI summary
A processor communication method is implemented by an electronic device including a first processor and a second processor. The method includes the operations as follows. The first processor transmits a first master interrupt signal to the second processor, in response to detecting a downlink packet. The first processor receives a first slave acknowledge signal returned from the second processor based on the first master interrupt signal. The first processor transmits the downlink packet to the second processor based on the first slave acknowledge signal, and transmits a second master interrupt signal after completion of the transmitting of the downlink packet. The second master interrupt signal is used to instruct the second processor to transmit a second slave acknowledge signal after completion of processing the downlink packet.