Reconfigurable Processor Compiler Path Extension
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Solution Overview
Problem
Reconfigurable microprocessors face inefficiencies due to delays in signal processing caused by asynchronous operational cells and reliance on estimated signal propagation delays, leading to reduced data processing speed and increased costs with faster clocks.
Innovation Solution
A method and compiler for reconfigurable processors that determine and extend signal processing paths to ensure the critical path terminates at an end-point cell, allowing for parallel implementation and reducing the need for all cells to be configurable as end-point cells, thereby minimizing overhead and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a global clock is used to trigger reconfiguration of signal processing paths, then the processor can maintain synchronous operation, but delays accumulate between signal processing completion and the next clock cycle, reducing processor efficiency
Solution Approach 1:
The patent implements feedback by having operational cells generate completion signals when signal processing is complete. These completion signals are fed back to the routing circuitry, which then triggers reconfiguration of the signal processing paths. This eliminates the need for global clock synchronization and allows immediate reconfiguration based on actual processing completion status, thereby maintaining synchronous operation while eliminating delays associated with clock cycles.
2Speed
If clock speed is increased to improve data processing speeds, then processing speed improves, but the cost increases and there are limits on how fast clocks can run
Solution Approach 1:
The feedback mechanism allows the processor to operate asynchronously with respect to global clock cycles. Operational cells can complete processing and generate completion signals at any time, and the routing circuitry responds immediately to these signals. This eliminates the need to increase clock speed to improve processing speed, as the system can reconfigure paths immediately based on actual completion status, thereby achieving high processing speeds without the costs and limitations associated with high-frequency clocks.
3Reliability
If estimated worst-case scenario signal propagation delays are used to determine when reconfiguration should occur, then the processor can ensure completion under all conditions, but this leads to unnecessary delays of one or more clock cycles
Solution Approach 1:
Instead of relying on estimated worst-case delays, the patent uses actual feedback signals from operational cells that indicate when processing is truly complete. This eliminates the need for conservative timing margins and allows the system to reconfigure immediately based on real completion status, thereby ensuring reliability while eliminating unnecessary delays associated with worst-case scenario planning.
4Measurement precision
If all operational cells are made configurable as end-point cells to enable trigger signal derivation, then accurate timing can be achieved, but the device complexity and overhead increase
Solution Approach 1:
The feedback mechanism allows any operational cell to serve as an end-point cell that generates completion signals. Rather than requiring all cells to be configurable as end-point cells with complex timing control logic, the system uses simple completion signal generation at the end of signal processing paths. This achieves accurate timing information while minimizing device complexity, as only the necessary end-point cells need to generate completion signals rather than all cells requiring full configurability.
Data Source
AI summary
The invention provides a method of compiling computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the method comprising: a routing step in which one or more signal processing paths are determined for performing one or more signal processing operations defined by the computer program instructions, each signal processing path comprising two or more of the operational cells connected via the programmable interconnect, the said signal processing paths being capable of implementation on the said operational cells and the said interconnect of the reconfigurable processor to perform the said one or more signal processing operations; and a post-routing step performed subsequent to the routing step in which an extended signal processing path is determined by extending one of the said signal processing paths determined in the routing step such that a critical path of the extended signal processing path is longer than a longest critical path of the signal processing paths determined in the routing step.