Processor Concurrent Core and Fabric Wake from Low Power State
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Solution Overview
Problem
Multicore processors face challenges in reducing latency when exiting low power states to handle interrupts efficiently, leading to increased power consumption and inefficiency in energy management.
Innovation Solution
Implementing an interrupt mechanism that allows concurrent waking of targeted cores and fabric structures, eliminating serialized low power state exit dependencies, thereby reducing latency and enabling deeper power state management with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor uses traditional low power state exit mechanisms, then power consumption is reduced during idle states, but latency increases when exiting to handle interrupts
Solution Approach 1:
The fabric is placed into a low power state preemptively before the core needs to exit, allowing the core to wake up faster without having to wait for fabric reinitialization. The fabric's low power state entry is performed in advance, decoupling the core's wake latency from fabric reinitialization time.
Solution Approach 2:
The system separates the core domain and fabric domain into independent power management units. The core can exit from low power state independently without being serialized by fabric reinitialization, achieving parallel wake-up paths that reduce overall exit latency.
2Use of energy by moving object
If the processor enters deeper low power states to save energy, then power consumption decreases, but the time to exit and respond to interrupts increases
Solution Approach 1:
The fabric enters low power state in advance before the core needs to respond to interrupts. This preliminary action allows the system to achieve deeper power savings while maintaining fast interrupt response, as the fabric is already in a low power state and does not need to reinitialize when the core wakes up.
3Device complexity
If the processor uses serialized low power state exit dependencies, then power management is simplified, but latency increases due to sequential wake-up requirements
Solution Approach 1:
The system divides power management into separate core domain and fabric domain controllers, each independently managing their respective components. This segmentation enables parallel power state transitions without complex interdependencies, reducing exit latency while maintaining manageable complexity through modular design.
Data Source
AI summary
In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.