Processor Control Flow Monitoring for Fast Error Detection
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Solution Overview
Problem
Existing control flow error detection techniques in software systems, particularly in embedded systems, suffer from performance overhead and limited error coverage, and traditional methods like watchdogs and redundancy approaches are inadequate for detecting transient hardware errors and control flow anomalies.
Innovation Solution
A hardware monitoring entity is closely associated with the processor to monitor control flow, using modified instruction set architecture (ISA) and watchdogs to detect control flow errors quickly and accurately, with mechanisms to verify correct block transitions and recover from errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-only monitoring solutions are used, then implementation flexibility is improved, but failure detection period increases
Solution Approach 1:
The system separates monitoring functionality into dedicated hardware monitoring entities that are closely coupled to specific processor cores, while software retains overall system control. This segmentation allows hardware to handle time-critical detection while software maintains flexibility in implementation and configuration.
Solution Approach 2:
Hardware monitoring entities act as intermediaries between the processor and the software monitoring system. These hardware entities capture control flow information directly from the processor pipeline and provide it to software, enabling fast detection without requiring software to poll or intercept every instruction execution.
2Speed
If hardware monitoring entities are introduced, then failure detection speed is improved, but device complexity increases
Solution Approach 1:
The hardware monitoring entities are designed to monitor multiple processor cores and handle various types of control flow exceptions (taken/not-taken, correct/incorrect targets). A single monitoring entity can service multiple cores, reducing the need for dedicated hardware per core and thereby limiting the increase in device complexity.
Solution Approach 2:
The monitoring entities are closely coupled to processor cores in a nested architecture where the monitoring logic is integrated near the core but remains a separate functional unit. This nesting allows the monitoring hardware to access core internals efficiently while maintaining a modular structure that limits overall system complexity.
3Device complexity
If traditional watchdog approaches are used, then implementation simplicity is improved, but error coverage decreases
Solution Approach 1:
The hardware monitoring entities continuously track control flow transitions and provide real-time feedback about taken and not-taken exceptions to both hardware exception handlers and software. This continuous feedback mechanism enables detection of a broader range of errors including transient hardware errors that traditional periodic watchdogs would miss.
Solution Approach 2:
The system pre-configures monitoring for specific control flow transitions and exception types before runtime errors occur. The hardware monitoring entities are set up to track relevant control flow information in advance, enabling immediate detection when errors occur rather than requiring post-error analysis or periodic checking.
Data Source
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AI summary
A mechanism is provided to monitor control flow failure of processors having a simple processing pipeline (e.g., RISC5) or accelerators (e.g., digital signal processors). Embodiments have a monitoring entity attached to the processor that does not interfere with the normal functionality of the accelerator. By virtue of being closely associated with the processor, the failure detection period can be smaller than that of a typical host watchdog and can be defined as per the needs of the application. In some embodiments, the failure detection period is defined by the number of clock cycles needed for the largest basic block in the executed code.