3D Processor Control Lists for Tile-Based Parallel Rendering
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Solution Overview
Problem
Conventional multimedia processors for image and video processing are computationally intensive and power-hungry, making them less suitable for mobile applications, which require efficient and high-performance solutions for tasks like 3D gaming and video encoding.
Innovation Solution
A system and method for controlling a 3D processor using a control list in memory, where processors generate control lists with primitive data and control information, enabling parallel processing of 3D graphics in a tile-based approach, with phases of tile binning and rendering, to manage data and control flow efficiently without external driver interaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional processors are used for image and video processing, then processing capability is sufficient, but power consumption is excessive
Solution Approach 1:
The patent segments the processing workload by dividing the frame buffer into multiple tiles and processing them in parallel using multiple processor cores. Each core handles specific tile regions, enabling divide-and-conquer approach that reduces power consumption per core while maintaining overall processing capability through parallel execution.
Solution Approach 2:
The patent introduces a tile-based dimensional organization of the frame buffer, transforming the traditional sequential processing approach into a parallel tile-processing model. This dimensional reorganization enables simultaneous processing of multiple image regions across different processor cores, optimizing the power-performance tradeoff.
2Productivity
If powerful processors and hardware accelerators are used, then processing performance is high, but device complexity increases
Solution Approach 1:
The patent implements a universal processor architecture that can handle multiple processing tasks (image processing, video encoding, 3D graphics) using the same tile-based parallel processing framework. This multi-functional approach eliminates the need for separate dedicated hardware accelerators for each task, reducing overall system complexity while maintaining high processing performance.
Solution Approach 2:
The system employs self-managing memory architecture where the memory controller automatically manages memory bandwidth allocation and data transfer between tiles without requiring complex external control. The processors independently manage their tile processing tasks, reducing the burden on system control mechanisms and simplifying overall system architecture.
3Quantity of substance
If large amounts of memory are used, then data capacity is sufficient, but memory bandwidth becomes a bottleneck
Solution Approach 1:
The patent segments the large frame buffer into smaller tile units that can be independently processed and cached. Each tile can be loaded into processor caches individually, reducing the total memory bandwidth requirement compared to loading entire large frames sequentially. This segmentation enables efficient data management while maintaining large data capacity.
Solution Approach 2:
The system performs preliminary tile identification and preparation before actual processing begins. By pre-organizing tiles and preparing their data in advance, the system optimizes memory access patterns and reduces runtime memory bandwidth demands, allowing efficient processing of large datasets without requiring proportionally large memory bandwidth.
Data Source
AI summary
A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device.