Dual Processor Coordination Fault Detection via Shared Memory
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Solution Overview
Problem
Current systems for coordinating the execution of tasks among multiple processors in electronic systems, such as aircraft computers, face challenges in ensuring reliable synchronization and detecting malfunctions in a timely and efficient manner, particularly due to asynchronous operations and complex synchronization requirements.
Innovation Solution
A method involving synchronized processors that record and compare identifiers for task execution periods, allowing for real-time monitoring and signaling of coordination faults, enabling reactive detection and transfer of tasks to backup systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DMA process is used for coordinating asynchronous processors, then coordination between processors is achieved, but the system complexity increases and implementation becomes difficult
Solution Approach 1:
The patent introduces a shared memory space as an intermediary between processors, where each processor writes its identifier during its time period. This mediator enables coordination and health verification without requiring complex direct communication protocols between processors, thus reducing implementation difficulty while maintaining reliability
Solution Approach 2:
The system implements feedback by having each processor read the identifier written by another processor and verify it matches the expected value. This feedback mechanism allows processors to confirm proper coordination and detect malfunctions through simple comparison operations, achieving reliable coordination without complex synchronization hardware
2Reliability
If consistency check device is used for detecting processor malfunction, then system reliability is improved, but the detection time is delayed
Solution Approach 1:
Each processor writes its identifier to shared memory as a preliminary action during its execution time period. This preliminary recording enables immediate verification by other processors without requiring additional checking operations, thus reducing detection time while maintaining reliable malfunction detection
Solution Approach 2:
The system maintains continuous monitoring by having processors constantly write and read identifiers in sequence. This continuous action ensures that any malfunction is detected immediately when the identifier mismatch occurs, rather than through periodic checks, eliminating detection delays while maintaining system reliability
3Device complexity
If master-slave principle is used for processor coordination, then coordination is simplified, but system reliability decreases due to single point of failure
Solution Approach 1:
The patent segments the coordination function by giving each processor equal capability to write and verify identifiers in shared memory. This segmentation eliminates the single point of failure in master-slave systems, as each processor can independently verify coordination, thus maintaining simple coordination mechanisms while improving system reliability through distributed verification
Data Source
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Figure 5A~5B
AI summary
A method for monitoring the coordinated execution of sequenced tasks by an electronic card comprising at least a first processor (PP1) and a second processor (PP2) synchronized on the same clock of determined time period, the method comprising: - a step of recording (11) in memory means (4) by the first processor (PP1) a first identifier (ID1) characterizing the time period (T1) during which the first sequenced task was executed; - a step of recording (12) in memory means (4) by the second processor (PP2) a second identifier (ID2) characterizing the time period (T1) during which the first accessory task (N1) was executed; - a step of comparison (13) by the first processor (PP1) of the first identifier (ID1) and the second identifier (ID2);and - a signaling step (15) by the first processor (PP1) in case of comparison failure in order to signal a coordination fault between the processors (PP1, PP2).;