Processor Core Bandwidth Allocation Mode Switching
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Solution Overview
Problem
Modern multi-core processors face inefficiencies in thread switching due to performance penalties, imprecise allocation of execution cycles, and challenges in predicting response times, especially when multiple threads compete for resources.
Innovation Solution
An event-based allocation mode switching system that uses a scheduler to detect events and select bandwidth allocation modes, allocating execution cycles among threads based on pre-configured modes stored in a bandwidth allocation table, allowing for precise and timely resource allocation without individual thread instruction changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single pipeline processor uses operating system to manage thread switching, then multi-thread processing is enabled, but performance penalty is incurred during thread changes
Solution Approach 1:
The processor is divided into multiple pipelines (first pipeline, second pipeline, etc.), each capable of independently executing different threads simultaneously. This segmentation eliminates the need for thread switching by allowing parallel execution of multiple threads in separate pipelines, thereby resolving the performance penalty associated with OS-managed thread switching while maintaining multi-thread processing capability.
2Productivity
If multiple pipelines are used to run multiple applications, then performance is improved, but power consumption and area increase substantially
Solution Approach 1:
The system dynamically configures the number and state of active pipelines based on workload requirements. Pipelines can be activated or deactivated as needed, allowing the processor to scale its resource usage according to actual demand. This dynamic approach maintains high performance when multiple threads are running while reducing power consumption when fewer threads are active, resolving the contradiction between performance improvement and power consumption increase.
3Adaptability or versatility
If cycle allocation is changed through processor instructions, then flexibility is achieved, but response time increases and predictability decreases
Solution Approach 1:
Cycle allocation parameters are pre-configured in dedicated registers before execution begins. The allocation mode register and thread-specific cycle count registers are set in advance, allowing the processor to immediately begin execution with the correct allocation parameters. This preliminary configuration eliminates the need for runtime instruction-based changes, thereby reducing response time and improving predictability while maintaining flexibility through the ability to pre-configure different allocation scenarios.
4Adaptability or versatility
If master thread reprograms cycle count, then cycle allocation can be changed, but it takes many cycles to finish reprogramming
Solution Approach 1:
Dedicated control registers serve as intermediaries between the master thread and the pipeline execution units. The allocation mode register and cycle count registers act as pre-configured storage locations that hold the desired allocation parameters. When the master thread needs to change cycle allocation, it simply writes to these registers rather than directly reprogramming each pipeline, which streamlines the reconfiguration process and reduces the number of cycles required compared to direct pipeline reprogramming.
5Loss of information
If polling or feedback techniques are used to get allocation feedback, then software can detect allocation state, but response time challenges and predictability are compromised
Solution Approach 1:
The system implements a dedicated feedback mechanism where the current allocation mode is continuously reflected in readable registers (allocation mode register and cycle count registers). Software can immediately read these registers to obtain accurate feedback about the current cycle allocation state without needing to poll or wait. This direct feedback approach provides real-time visibility into allocation status, eliminating the delays and predictability issues associated with polling techniques while maintaining full information about the allocation state.
Data Source
AI summary
A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.