Processor Core Burn-In Testing with Uniform Power Distribution
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Solution Overview
Problem
Multiprocessor chips require separate voltage planes for each processor core to optimize performance, increasing complexity and cost, while using a single voltage plane sub-optimizes core performance due to varying power requirements across cores.
Innovation Solution
A computer-implemented method selects a set of processor cores based on power management data to achieve uniform power and thermal distribution during burn-in testing, using either separate voltage pins or an on-chip network and gating system to regulate voltage across cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If separate voltage planes are used for each processor core, then performance is optimized, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple voltage plane control functions into a single unified voltage plane. Instead of providing separate voltage planes for each processor core, the invention uses one voltage plane to power all cores, thereby reducing device complexity and cost while maintaining the ability to optimize performance through selective core activation and clock gating mechanisms.
2Device complexity
If a single voltage plane is used, then device complexity is reduced, but performance is sub-optimized due to varying power requirements
Solution Approach 1:
The patent implements dynamic control mechanisms including selective core activation and clock gating that allow the single voltage plane to adapt to varying power requirements of different processor cores. This dynamic approach enables performance optimization by activating only the necessary cores and controlling their clock signals, thereby compensating for the lack of separate voltage planes.
3Loss of time
If all processor cores are tested simultaneously during burn-in, then testing time is reduced, but power distribution becomes non-uniform causing thermal issues
Solution Approach 1:
The patent segments the processor cores into different groups or sets for staged burn-in testing. Instead of activating all cores simultaneously, the invention divides them into multiple groups that are tested in sequence or in controlled combinations. This segmentation approach ensures uniform power distribution and prevents thermal issues while maintaining efficient testing throughput.
Solution Approach 2:
The patent implements periodic activation patterns during burn-in testing, where processor cores are activated in alternating groups or cycles. This periodic action allows thermal management between testing phases while maintaining overall testing efficiency, preventing the thermal accumulation that would occur with continuous full-core activation.
Data Source
AI summary
A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.