Processor Core Debugging via Logical Identifier Virtualization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuits, such as system on a chip (SoC) devices, leads to higher manufacturing costs due to lower yields, as defective processor cores render devices less functional, necessitating a method to configure and sell these devices as less complex systems while masking defective cores from external interfaces.
Innovation Solution
A circuit with a broadcaster module, decoder units, and an aggregator module that uses logical identifiers to bypass defective processor cores during debugging, allowing the system to be configured and sold with fewer active cores, thereby improving manufacturing yield by virtualizing the identifier of each processor core and enabling the system to be presented as having fewer cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If each processor core is tested and verified individually to identify defective cores, then manufacturing yield can be improved by configuring defective devices as less complex systems, but the device complexity and manufacturing cost increase due to the need for additional testing infrastructure and reconfiguration capabilities
Solution Approach 1:
The patent introduces a broadcaster module as an intermediary component that receives debug requests and distributes them to multiple processor cores through a bus system. This intermediary architecture allows centralized testing control while maintaining individual core accessibility, enabling yield improvement through systematic testing without proportionally increasing overall system complexity
Solution Approach 2:
The patent segments the testing function by introducing separate decoder units for each processor core that can independently decode and respond to debug requests. This segmentation allows parallel testing of multiple cores through a single broadcaster, improving testing efficiency and manufacturing yield without linearly increasing the complexity of the testing infrastructure
2Ease of manufacture
If defective cores are masked from external interfaces by assigning logical identifiers only to functional cores, then the system can be sold as a less complex system with fewer active cores, but the addressing mechanism becomes more complex requiring logical identifier translation
Solution Approach 1:
The patent creates a logical copy of the physical core identifiers by assigning logical identifiers to functional cores. This copying mechanism allows the system to present a simplified view to external interfaces while maintaining the physical reality of multiple cores, enabling defective devices to be sold as less complex systems without requiring complex addressing translation logic
Solution Approach 2:
The decoder units act as intermediaries between the logical identifier space and the physical core addresses. Each decoder unit receives logical identifiers and translates them to the appropriate physical core addresses, masking the complexity of defective core management from external interfaces while maintaining efficient addressing through the logical identifier mechanism
3Loss of time
If a broadcaster module is used to distribute debug requests to multiple processor cores via a bus, then debugging efficiency improves by enabling parallel access to multiple cores, but the manufacturing cost and device complexity increase due to additional hardware components
Solution Approach 1:
The broadcaster module is designed as a universal component that can distribute debug requests to multiple processor cores through a shared bus infrastructure. This multi-functional design allows a single broadcaster to serve multiple cores simultaneously, improving debugging efficiency and reducing debugging time without proportionally increasing device complexity through repeated dedicated interfaces for each core
Data Source
AI summary
A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.