Processor Core Early Commit Logic for Store-Conditional Latency
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Solution Overview
Problem
In shared memory multiprocessor systems, the communication latency between processor cores and lower level caches slows down the processing of store-conditional instructions and dependent instructions due to the need for systemwide coherence, which affects the efficiency of data access synchronization.
Innovation Solution
The solution involves allowing store-conditional requests to commit updates directly in the processor core before transmitting them to the point of systemwide coherence, enabling early completion of store-conditional instructions and reducing latency by using a processor core with an upper level cache, execution unit, and completion logic that checks a flag to determine if the request can be completed early.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If store-conditional requests are transmitted to lower level cache for systemwide coherence determination, then coherence correctness is ensured, but processing speed deteriorates due to communication latency
Solution Approach 1:
The processor core performs preliminary action by committing the store-conditional update locally before transmitting the request to the lower level cache. The completion logic determines early completion based on whether any processor has reserved the target address, allowing the instruction to complete ahead of the coherence determination. This preliminary local commitment resolves the contradiction by enabling fast processing while maintaining correctness through subsequent coherence validation.
2Reliability
If store-conditional instructions wait for lower level cache determination, then systemwide coherence is maintained, but productivity decreases due to latency
Solution Approach 1:
The system performs preliminary coherence checking by having the completion logic determine if early completion is permissible based on reservation status. This allows productive instructions to proceed without waiting for full cache determination, while still maintaining systemwide coherence through the reservation mechanism that prevents conflicting updates.
Solution Approach 2:
The completion logic acts as an intermediary between the execution unit and the lower level cache. It intercepts store-conditional requests and makes local determination of early completion based on reservation information, eliminating the need for instructions to wait for cache determination while preserving coherence through the reservation system.
3Loss of time
If early commitment is allowed in processor core, then processing latency is reduced, but device complexity increases due to completion logic and flag management
Solution Approach 1:
The processor core provides self-service by implementing completion logic that autonomously determines whether early commitment is safe based on reservation status. The execution unit sets completion flags when addresses are reserved, and the completion logic uses these flags to make local determination of early completion, eliminating the need for complex external coordination while reducing latency.
Data Source
AI summary
A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.