Processor-Core ECC Fault Injection for ASIL Coverage
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Solution Overview
Problem
Existing safety protocols in automotive systems, such as ISO 26262, require high fault detection and correction capabilities, but existing fault emulation methods are inefficient and costly in terms of semiconductor area, especially when implemented at multiple interconnects within a System-on-Chip (SoC).
Innovation Solution
Implementing fault emulation logic at the processor core instead of or in addition to interconnects, manipulating Error Correcting Code (ECC) data to emulate faults, thereby reducing the need for duplicate logic at interconnects and optimizing semiconductor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault emulation logic is implemented at multiple interconnects within an SoC, then fault detection coverage is improved, but semiconductor area usage increases
Solution Approach 1:
The patent consolidates fault emulation functionality into a single processor core rather than distributing it across multiple interconnects. The processor core generates error correction codes and intentionally introduces faults into data signals, while a single error detection circuit at the destination intercepts and analyzes all fault conditions. This merging approach maintains comprehensive fault detection coverage while eliminating redundant fault emulation logic at multiple interconnect locations, thereby reducing overall semiconductor area usage.
Solution Approach 2:
The processor core is designed to perform multiple functions: normal data processing, error correction code generation, and fault emulation. By making the processor core universal and capable of handling fault injection tasks, the system eliminates the need for dedicated fault emulation circuits at each interconnect, reducing total semiconductor area while maintaining fault detection capabilities.
2Reliability
If fault emulation is implemented at interconnects, then fault detection capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts fault emulation functionality from multiple interconnect locations and consolidates it into the processor core. This extraction eliminates redundant hardware complexity at interconnects while preserving the essential fault detection capability through centralized error correction code generation and a single error detection circuit at the destination.
Data Source
AI summary
A system includes fault emulation testing circuitry. The system may implement the fault emulation testing circuitry in a processing core, rather than in an interconnect. The fault emulation testing circuitry may inject a fault into an error correction hash.